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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00

par_masters: Reshuffle to remove forward declarations

Dispense with all these forward declarations by way of
ordering. Just deal with all the par_masters in one go
to be over and done with.

BUG=none
BRANCH=none
TEST=builds

Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Edward O'Callaghan
2021-05-24 20:33:45 +10:00
committed by Edward O'Callaghan
parent 4f53772103
commit ad8eb60e5d
11 changed files with 258 additions and 293 deletions

View File

@ -40,9 +40,19 @@ const struct dev_entry ata_hpt[] = {
};
static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr);
chipaddr addr)
{
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
OUTB(val, io_base_addr + BIOS_ROM_DATA);
}
static uint8_t atahpt_chip_readb(const struct flashctx *flash,
const chipaddr addr);
const chipaddr addr)
{
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
return INB(io_base_addr + BIOS_ROM_DATA);
}
static const struct par_master par_master_atahpt = {
.chip_readb = atahpt_chip_readb,
.chip_readw = fallback_chip_readw,
@ -80,20 +90,6 @@ int atahpt_init(void)
return 0;
}
static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr)
{
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
OUTB(val, io_base_addr + BIOS_ROM_DATA);
}
static uint8_t atahpt_chip_readb(const struct flashctx *flash,
const chipaddr addr)
{
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
return INB(io_base_addr + BIOS_ROM_DATA);
}
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif