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Code Issues Releases Wiki Activity

par_masters: Reshuffle to remove forward declarations

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Dispense with all these forward declarations by way of
ordering. Just deal with all the par_masters in one go
to be over and done with.

BUG=none
BRANCH=none
TEST=builds

Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Edward O'Callaghan
2021-05-24 20:33:45 +10:00
committed by Edward O'Callaghan
parent 4f53772103
commit ad8eb60e5d
11 changed files with 258 additions and 293 deletions
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70
satamv.c
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@ -38,10 +38,41 @@ const struct dev_entry satas_mv[] = {
#define PCI_BAR2_CONTROL 0x00c08
#define GPIO_PORT_CONTROL 0x104f0
/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
* If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
* This code only supports indirect accesses for now.
*/
/* Indirect access to via the I/O BAR1. */
static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
{
/* 0x80000000 selects BAR2 for remapping. */
OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
}
/* Indirect access to via the I/O BAR1. */
static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
{
/* 0x80000000 selects BAR2 for remapping. */
OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
return INB(mv_iobar + 0x80 + (addr & 0x3));
}
/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr);
chipaddr addr)
{
satamv_indirect_chip_writeb(val, addr);
}
/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
static uint8_t satamv_chip_readb(const struct flashctx *flash,
const chipaddr addr);
const chipaddr addr)
{
return satamv_indirect_chip_readb(addr);
}
static const struct par_master par_master_satamv = {
.chip_readb = satamv_chip_readb,
.chip_readw = fallback_chip_readw,
@ -153,41 +184,6 @@ int satamv_init(void)
return 0;
}
/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
* If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
* This code only supports indirect accesses for now.
*/
/* Indirect access to via the I/O BAR1. */
static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
{
/* 0x80000000 selects BAR2 for remapping. */
OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
}
/* Indirect access to via the I/O BAR1. */
static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
{
/* 0x80000000 selects BAR2 for remapping. */
OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
return INB(mv_iobar + 0x80 + (addr & 0x3));
}
/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr)
{
satamv_indirect_chip_writeb(val, addr);
}
/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
static uint8_t satamv_chip_readb(const struct flashctx *flash,
const chipaddr addr)
{
return satamv_indirect_chip_readb(addr);
}
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif