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https://review.coreboot.org/flashrom.git
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Move SB600 SPI initialization to sb600spi.c
Corresponding to flashrom svn r1099. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Michael Karcher
parent
a4448d9aec
commit
b05b9e100a
@ -693,10 +693,9 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
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static int enable_flash_sb600(struct pci_dev *dev, const char *name)
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{
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uint32_t tmp, prot;
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uint32_t prot;
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uint8_t reg;
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struct pci_dev *smbus_dev;
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int has_spi = 1;
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int ret;
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/* Clear ROM protect 0-3. */
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for (reg = 0x50; reg < 0x60; reg += 4) {
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@ -720,80 +719,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
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(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
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}
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/* Read SPI_BaseAddr */
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tmp = pci_read_long(dev, 0xa0);
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tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
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msg_pdbg("SPI base address is at 0x%x\n", tmp);
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/* If the BAR has address 0, it is unlikely SPI is used. */
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if (!tmp)
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has_spi = 0;
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if (has_spi) {
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/* Physical memory has to be mapped at page (4k) boundaries. */
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sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
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0x1000);
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/* The low bits of the SPI base address are used as offset into
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* the mapped page.
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*/
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sb600_spibar += tmp & 0xfff;
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tmp = pci_read_long(dev, 0xa0);
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msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
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"AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
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(tmp & 0x4) >> 2);
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tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
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msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp);
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tmp = pci_read_byte(dev, 0xbb);
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msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
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tmp & 0x1, (tmp & 0x20) >> 5);
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tmp = mmio_readl(sb600_spibar);
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msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
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"SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
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"SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
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(tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
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(tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
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(tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
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}
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/* Look for the SMBus device. */
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smbus_dev = pci_dev_find(0x1002, 0x4385);
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if (has_spi && !smbus_dev) {
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msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
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has_spi = 0;
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}
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if (has_spi) {
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/* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
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/* GPIO11/SPI_DO and GPIO12/SPI_DI status */
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reg = pci_read_byte(smbus_dev, 0xAB);
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reg &= 0xC0;
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msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
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msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
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if (reg != 0x00)
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has_spi = 0;
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/* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
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reg = pci_read_byte(smbus_dev, 0x83);
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reg &= 0xC0;
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msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
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msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
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/* SPI_HOLD is not used on all boards, filter it out. */
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if ((reg & 0x80) != 0x00)
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has_spi = 0;
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/* GPIO47/SPI_CLK status */
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reg = pci_read_byte(smbus_dev, 0xA7);
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reg &= 0x40;
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msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
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if (reg != 0x00)
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has_spi = 0;
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}
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buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
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if (has_spi) {
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buses_supported |= CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_SB600;
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}
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ret = sb600_probe_spi(dev);
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/* Read ROM strap override register. */
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OUTB(0x8f, 0xcd6);
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@ -830,7 +758,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
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OUTB(0x0e, 0xcd7);
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*/
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return 0;
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return ret;
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}
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static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
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2
flash.h
2
flash.h
@ -719,11 +719,11 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int
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int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
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/* sb600spi.c */
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int sb600_probe_spi(struct pci_dev *dev);
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int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
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int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
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extern uint8_t *sb600_spibar;
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/* wbsio_spi.c */
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int wbsio_check_for_spi(void);
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84
sb600spi.c
84
sb600spi.c
@ -40,7 +40,7 @@
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*};
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*/
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uint8_t *sb600_spibar = NULL;
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static uint8_t *sb600_spibar = NULL;
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int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
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{
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@ -152,4 +152,86 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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return 0;
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}
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int sb600_probe_spi(struct pci_dev *dev)
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{
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struct pci_dev *smbus_dev;
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uint32_t tmp;
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uint8_t reg;
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/* Read SPI_BaseAddr */
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tmp = pci_read_long(dev, 0xa0);
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tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
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msg_pdbg("SPI base address is at 0x%x\n", tmp);
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/* If the BAR has address 0, it is unlikely SPI is used. */
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if (!tmp)
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return 0;
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/* Physical memory has to be mapped at page (4k) boundaries. */
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sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
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0x1000);
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/* The low bits of the SPI base address are used as offset into
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* the mapped page.
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*/
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sb600_spibar += tmp & 0xfff;
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tmp = pci_read_long(dev, 0xa0);
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msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
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"AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
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(tmp & 0x4) >> 2);
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tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
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msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp);
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tmp = pci_read_byte(dev, 0xbb);
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msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
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tmp & 0x1, (tmp & 0x20) >> 5);
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tmp = mmio_readl(sb600_spibar);
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msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
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"SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
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"SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
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(tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
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(tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
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(tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
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/* Look for the SMBus device. */
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smbus_dev = pci_dev_find(0x1002, 0x4385);
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if (!smbus_dev) {
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msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
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return ERROR_NONFATAL;
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}
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/* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
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/* GPIO11/SPI_DO and GPIO12/SPI_DI status */
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reg = pci_read_byte(smbus_dev, 0xAB);
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reg &= 0xC0;
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msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
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msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
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if (reg != 0x00) {
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msg_pdbg("Not enabling SPI");
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return 0;
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}
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/* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
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reg = pci_read_byte(smbus_dev, 0x83);
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reg &= 0xC0;
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msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
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msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
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/* SPI_HOLD is not used on all boards, filter it out. */
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if ((reg & 0x80) != 0x00) {
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msg_pdbg("Not enabling SPI");
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return 0;
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}
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/* GPIO47/SPI_CLK status */
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reg = pci_read_byte(smbus_dev, 0xA7);
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reg &= 0x40;
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msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
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if (reg != 0x00) {
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msg_pdbg("Not enabling SPI");
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return 0;
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}
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buses_supported |= CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_SB600;
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return 0;
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}
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#endif
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