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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 14:33:18 +02:00

Add support for parallel flash on Dr. Kaiser PC-Waechter PCI devices

The vendor sold different designs under that name, the patch works with
the one that has an Actel FPGA as PCI-to-Flash bridge.

The Flash chip is a "Macronix MX29F001B" (128 KB, parallel) soldered
directly to the PCB.
Flash operations (PROBE, READ, ERASE, WRITE) work as expected.

Corresponding to flashrom svn r712.

Signed-off-by: TURBO J <turboj@gmx.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
TURBO J
2009-09-02 23:00:46 +00:00
committed by Uwe Hermann
parent 04aa59a864
commit b0912c0adb
7 changed files with 41 additions and 11 deletions

12
flash.h
View File

@ -84,6 +84,7 @@ enum programmer {
PROGRAMMER_INTERNAL,
PROGRAMMER_DUMMY,
PROGRAMMER_NIC3COM,
PROGRAMMER_DRKAISER,
PROGRAMMER_SATASII,
PROGRAMMER_IT87SPI,
#if FT2232_SPI_SUPPORT == 1
@ -281,8 +282,8 @@ struct pcidev_status {
const char *vendor_name;
const char *device_name;
};
uint32_t pcidev_validate(struct pci_dev *dev, struct pcidev_status *devs);
uint32_t pcidev_init(uint16_t vendor_id, struct pcidev_status *devs, char *pcidev_bdf);
uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs);
uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf);
/* print.c */
char *flashbuses_to_text(enum chipbustype bustype);
@ -387,6 +388,13 @@ void nic3com_chip_writeb(uint8_t val, chipaddr addr);
uint8_t nic3com_chip_readb(const chipaddr addr);
extern struct pcidev_status nics_3com[];
/* drkaiser.c */
int drkaiser_init(void);
int drkaiser_shutdown(void);
void drkaiser_chip_writeb(uint8_t val, chipaddr addr);
uint8_t drkaiser_chip_readb(const chipaddr addr);
extern struct pcidev_status drkaiser_pcidev[];
/* satasii.c */
int satasii_init(void);
int satasii_shutdown(void);