openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-29 07:53:44 +02:00
Code Issues Releases Wiki Activity

chipset_enable.c: Mark Skylake U Premium as DEP

Browse Source 
Tested reading, writing and erasing the internal flash chip using an
Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.

Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Angel Pons 2020-02-29 23:13:43 +01:00 committed by Nico Huber
parent 3e67cb7b78
commit b1e558389a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chipset_enable.c
View File

@ -1987,7 +1987,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100},
{0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100},
{0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100},
{0x8086, 0x9d48, B_S, NT, "Intel", "Skylake U Premium", enable_flash_pch100},
{0x8086, 0x9d48, B_S, DEP, "Intel", "Skylake U Premium", enable_flash_pch100},
{0x8086, 0x9d4b, B_S, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100},
{0x8086, 0x9d4e, B_S, DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100},
{0x8086, 0x9d50, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100},