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Add support for Comet Lake-U/400-series PCH

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Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically
to CHIPSET_300_SERIES_CANNON_POINT.

Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT.

Test: read/write unlocked CML-U board

Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Matt DeVillier
2020-08-12 12:48:06 -05:00
committed by Angel Pons
parent cb9f3cd0a7
commit b1f858f65b
5 changed files with 32 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
chipset_enable.c
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@ -599,6 +599,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc);
@ -694,6 +695,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
boot_straps = boot_straps_pch8_lp;
break;
case CHIPSET_APOLLO_LAKE:
@ -722,6 +724,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
bbs = (gcs >> 6) & 0x1;
break;
@ -963,6 +966,11 @@ static int enable_flash_pch300(struct pci_dev *const dev, const char *const name
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
}
static int enable_flash_pch400(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT);
}
static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
@ -2004,6 +2012,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100},
{0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100},
{0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
{0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400},
{0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100},