openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-26 22:52:34 +02:00
Code Issues Releases Wiki Activity

flashchips: add GD25B512MF and GD25R512MF

Browse Source 
GD25B512MF: 3V 512Mbit, QE = 1
GD25R512MF: GD25B512MF feature + RPMC
These two part share the same datasheet on the flash side.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-00975-GD25B512MF-Rev1.1.pdf

Tested both models on ch347 with erase, write, read, and protection.

Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84083
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Victor Lim 2024-08-25 00:37:59 -07:00 committed by Anastasia Klimchuk
parent 00e02a6184
commit b2a35e1bd4
2 changed files with 57 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
flashchips.c
View File

@ -7636,6 +7636,62 @@ const struct flashchip flashchips[] = {
.decode_range = DECODE_RANGE_SPI25,
},
{
.vendor = "GigaDevice",
.name = "GD25B512MF/GD25R512MF",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25B512MF,
.total_size = 65536,
.page_size = 256,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_4BA,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 16384} },
.block_erase = SPI_BLOCK_ERASE_21,
}, {
.eraseblocks = { {4 * 1024, 16384} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_5C,
}, {
.eraseblocks = { {32 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_DC,
}, {
.eraseblocks = { {64 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {64 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {64 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
.unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.srl = {STATUS2, 6, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
.cmp = {STATUS3, 3, RW},
},
.decode_range = DECODE_RANGE_SPI25,
},
{
.vendor = "GigaDevice",
.name = "GD25Q32(B)",

1
include/flashchips.h
View File

@ -396,6 +396,7 @@
#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */
#define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */
#define GIGADEVICE_GD25B512MF 0x401A /* Same as GD25R512MF */
#define GIGADEVICE_GD25VQ21B 0x4212
#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */
#define GIGADEVICE_GD25VQ80C 0x4214