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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 06:23:18 +02:00

Intel NIC with parallel flash support

Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com>

Corresponding to flashrom svn r1297.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Carl-Daniel Hailfinger
2011-05-08 00:24:18 +00:00
parent 064bbc9f37
commit b713d2e35c
6 changed files with 163 additions and 3 deletions

View File

@ -67,6 +67,9 @@ enum programmer {
#if CONFIG_RAYER_SPI == 1
PROGRAMMER_RAYER_SPI,
#endif
#if CONFIG_NICINTEL == 1
PROGRAMMER_NICINTEL,
#endif
#if CONFIG_NICINTEL_SPI == 1
PROGRAMMER_NICINTEL_SPI,
#endif
@ -232,7 +235,7 @@ int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
#endif
/* print.c */
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
void print_supported_pcidevs(const struct pcidev_status *devs);
#endif
@ -420,6 +423,15 @@ uint8_t nicnatsemi_chip_readb(const chipaddr addr);
extern const struct pcidev_status nics_natsemi[];
#endif
/* nicintel.c */
#if CONFIG_NICINTEL == 1
int nicintel_init(void);
int nicintel_shutdown(void);
void nicintel_chip_writeb(uint8_t val, chipaddr addr);
uint8_t nicintel_chip_readb(const chipaddr addr);
extern const struct pcidev_status nics_intel[];
#endif
/* nicintel_spi.c */
#if CONFIG_NICINTEL_SPI == 1
int nicintel_spi_init(void);