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spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status register and enables it on a limited set of flash chips. Chip support for RDSR2/WRSR2/extended WRSR is represented using feature flags to be consistent with how other SPI capabilities are represented. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series TEST=logged SR2 read/write values during wp commands Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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committed by
Anastasia Klimchuk

parent
a0319804a0
commit
b7ea3a9a5d
@ -6317,7 +6317,7 @@ const struct flashchip flashchips[] = {
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.total_size = 16384,
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.page_size = 256,
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -6706,7 +6706,8 @@ const struct flashchip flashchips[] = {
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.model_id = GIGADEVICE_GD25Q256D,
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.total_size = 32768,
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.page_size = 256,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN |
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FEATURE_WRSR_EXT | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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@ -6754,7 +6755,7 @@ const struct flashchip flashchips[] = {
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.total_size = 4096,
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.page_size = 256,
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/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2,
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.tested = TEST_OK_PREW,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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