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spi25_statusreg,flashchips: add SR2 read/write support

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This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.

Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.

BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands

Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Nikolai Artemiev
2021-10-20 22:32:25 +11:00
committed by Anastasia Klimchuk
parent a0319804a0
commit b7ea3a9a5d
4 changed files with 53 additions and 3 deletions
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11
spi.h
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@ -131,6 +131,11 @@
#define JEDEC_RDSR_OUTSIZE 0x01
#define JEDEC_RDSR_INSIZE 0x01
/* Read Status Register 2 */
#define JEDEC_RDSR2 0x35
#define JEDEC_RDSR2_OUTSIZE 0x01
#define JEDEC_RDSR2_INSIZE 0x01
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
@ -146,6 +151,12 @@
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02
#define JEDEC_WRSR_INSIZE 0x00
#define JEDEC_WRSR_EXT_OUTSIZE 0x03
/* Write Status Register 2 */
#define JEDEC_WRSR2 0x31
#define JEDEC_WRSR2_OUTSIZE 0x02
#define JEDEC_WRSR2_INSIZE 0x00
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7