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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00

Kill central list of SPI programmers

Remove the array spi_programmer, replace it by dynamic registration
instead. Also initially start with no busses supported, and switch to
the default non-SPI only for the internal programmer.

Also this patch changes the initialization for the buses_supported variable
from "everything-except-SPI" to "nothing". All programmers have to set the
bus type on their own, and this enables register_spi_programmer to just add
the SPI both for on-board SPI interfaces (where the internal programmer
already detected the other bus types), as well as for external programmers
(where we have the default "none").

Corresponding to flashrom svn r1299.

Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Michael Karcher
2011-05-11 17:07:07 +00:00
parent 627975196d
commit b9dbe48b77
19 changed files with 222 additions and 282 deletions

View File

@ -60,6 +60,19 @@ static int emu_jedec_ce_c7_size = 0;
static int spi_write_256_chunksize = 256;
static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr);
static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
static const struct spi_programmer spi_programmer_dummyflasher = {
.type = SPI_CONTROLLER_DUMMY,
.max_data_read = MAX_DATA_READ_UNLIMITED,
.max_data_write = MAX_DATA_UNSPECIFIED,
.command = dummy_spi_send_command,
.multicommand = default_spi_send_multicommand,
.read = default_spi_read,
.write_256 = dummy_spi_write_256,
};
int dummy_init(void)
{
char *bustext = NULL;
@ -91,8 +104,7 @@ int dummy_init(void)
msg_pdbg("Enabling support for %s flash.\n", "FWH");
}
if (strstr(bustext, "spi")) {
buses_supported |= CHIP_BUSTYPE_SPI;
spi_controller = SPI_CONTROLLER_DUMMY;
register_spi_programmer(&spi_programmer_dummyflasher);
msg_pdbg("Enabling support for %s flash.\n", "SPI");
}
if (buses_supported == CHIP_BUSTYPE_NONE)
@ -471,7 +483,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt
}
#endif
int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int i;
@ -507,7 +519,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return 0;
}
int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
{
return spi_write_chunked(flash, buf, start, len,
spi_write_256_chunksize);