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https://review.coreboot.org/flashrom.git
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Add a dummy SPI controller driver, similar to the dummy LPC/FWH/Parallel flasher driver
Does not support reading or writing the fake chip yet. flashrom --programmer dummy also enables the dummy SPI controller driver. Testing the dummy SPI driver revealed a RDID debug printing bug in the SPI core. Fix that as well. Corresponding to flashrom svn r507. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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@ -31,6 +31,7 @@
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int dummy_init(void)
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int dummy_init(void)
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{
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{
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printf_debug("%s\n", __func__);
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printf_debug("%s\n", __func__);
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flashbus = BUS_TYPE_DUMMY_SPI;
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return 0;
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return 0;
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}
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}
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@ -86,3 +87,23 @@ uint32_t dummy_chip_readl(const volatile void *addr)
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return 0xffffffff;
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return 0xffffffff;
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}
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}
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int dummy_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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int i;
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printf_debug("%s:", __func__);
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printf_debug(" writing %u bytes:", writecnt);
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for (i = 0; i < writecnt; i++)
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printf_debug(" 0x%02x", writearr[i]);
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printf_debug(" reading %u bytes:", readcnt);
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for (i = 0; i < readcnt; i++) {
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printf_debug(" 0xff");
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readarr[i] = 0xff;
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}
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printf_debug("\n");
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return 0;
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}
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5
flash.h
5
flash.h
@ -571,7 +571,8 @@ typedef enum {
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BUS_TYPE_IT87XX_SPI,
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BUS_TYPE_IT87XX_SPI,
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BUS_TYPE_SB600_SPI,
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BUS_TYPE_SB600_SPI,
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BUS_TYPE_VIA_SPI,
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BUS_TYPE_VIA_SPI,
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BUS_TYPE_WBSIO_SPI
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BUS_TYPE_WBSIO_SPI,
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BUS_TYPE_DUMMY_SPI
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} flashbus_t;
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} flashbus_t;
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extern flashbus_t flashbus;
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extern flashbus_t flashbus;
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@ -602,6 +603,8 @@ void dummy_chip_writel(uint32_t val, volatile void *addr);
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uint8_t dummy_chip_readb(const volatile void *addr);
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uint8_t dummy_chip_readb(const volatile void *addr);
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uint16_t dummy_chip_readw(const volatile void *addr);
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uint16_t dummy_chip_readw(const volatile void *addr);
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uint32_t dummy_chip_readl(const volatile void *addr);
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uint32_t dummy_chip_readl(const volatile void *addr);
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int dummy_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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/* nic3com.c */
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/* nic3com.c */
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int nic3com_init(void);
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int nic3com_init(void);
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10
spi.c
10
spi.c
@ -46,6 +46,8 @@ int spi_command(unsigned int writecnt, unsigned int readcnt,
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return sb600_spi_command(writecnt, readcnt, writearr, readarr);
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return sb600_spi_command(writecnt, readcnt, writearr, readarr);
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case BUS_TYPE_WBSIO_SPI:
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case BUS_TYPE_WBSIO_SPI:
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return wbsio_spi_command(writecnt, readcnt, writearr, readarr);
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return wbsio_spi_command(writecnt, readcnt, writearr, readarr);
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case BUS_TYPE_DUMMY_SPI:
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return dummy_spi_command(writecnt, readcnt, writearr, readarr);
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default:
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default:
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printf_debug
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printf_debug
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("%s called, but no SPI chipset/strapping detected\n",
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("%s called, but no SPI chipset/strapping detected\n",
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@ -58,12 +60,15 @@ static int spi_rdid(unsigned char *readarr, int bytes)
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{
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{
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const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
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const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
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int ret;
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int ret;
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int i;
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ret = spi_command(sizeof(cmd), bytes, cmd, readarr);
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ret = spi_command(sizeof(cmd), bytes, cmd, readarr);
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if (ret)
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if (ret)
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return ret;
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return ret;
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printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
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printf_debug("RDID returned");
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readarr[2]);
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for (i = 0; i < bytes; i++)
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printf_debug(" 0x%02x", readarr[i]);
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printf_debug("\n");
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return 0;
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return 0;
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}
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}
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@ -202,6 +207,7 @@ int probe_spi_rdid4(struct flashchip *flash)
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case BUS_TYPE_VIA_SPI:
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case BUS_TYPE_VIA_SPI:
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case BUS_TYPE_SB600_SPI:
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case BUS_TYPE_SB600_SPI:
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case BUS_TYPE_WBSIO_SPI:
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case BUS_TYPE_WBSIO_SPI:
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case BUS_TYPE_DUMMY_SPI:
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return probe_spi_rdid_generic(flash, 4);
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return probe_spi_rdid_generic(flash, 4);
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default:
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default:
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printf_debug("4b ID not supported on this SPI controller\n");
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printf_debug("4b ID not supported on this SPI controller\n");
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