diff --git a/Makefile b/Makefile index 18c5a6b3a..2e774df5e 100644 --- a/Makefile +++ b/Makefile @@ -113,6 +113,9 @@ CONFIG_DRKAISER ?= yes # Always enable Realtek NICs for now. CONFIG_NICREALTEK ?= yes +# Disable National Semiconductor NICs until support is complete and tested. +CONFIG_NICNATSEMI ?= no + # Always enable Bus Pirate SPI for now. CONFIG_BUSPIRATE_SPI ?= yes @@ -192,6 +195,12 @@ PROGRAMMER_OBJS += nicrealtek.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICNATSEMI), yes) +FEATURE_CFLAGS += -D'CONFIG_NICNATSEMI=1' +PROGRAMMER_OBJS += nicnatsemi.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_BUSPIRATE_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BUSPIRATE_SPI=1' PROGRAMMER_OBJS += buspirate_spi.o diff --git a/flash.h b/flash.h index 9d92db25f..13f7981bb 100644 --- a/flash.h +++ b/flash.h @@ -49,6 +49,9 @@ enum programmer { PROGRAMMER_NICREALTEK, PROGRAMMER_NICREALTEK2, #endif +#if CONFIG_NICNATSEMI == 1 + PROGRAMMER_NICNATSEMI, +#endif #if CONFIG_GFXNVIDIA == 1 PROGRAMMER_GFXNVIDIA, #endif @@ -339,7 +342,7 @@ uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *dev /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 void print_supported_pcidevs(struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -491,6 +494,14 @@ extern struct pcidev_status nics_realtek[]; extern struct pcidev_status nics_realteksmc1211[]; #endif +/* nicnatsemi.c */ +#if CONFIG_NICNATSEMI == 1 +int nicnatsemi_init(void); +int nicnatsemi_shutdown(void); +void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); +uint8_t nicnatsemi_chip_readb(const chipaddr addr); +extern struct pcidev_status nics_natsemi[]; +#endif /* satasii.c */ #if CONFIG_SATASII == 1 diff --git a/flashrom.c b/flashrom.c index 73145a9a7..0f51979ae 100644 --- a/flashrom.c +++ b/flashrom.c @@ -48,7 +48,7 @@ enum programmer programmer = PROGRAMMER_DUMMY; * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -59,6 +59,9 @@ enum programmer programmer = PROGRAMMER_NICREALTEK PROGRAMMER_NICREALTEK2 #endif +#if CONFIG_NICNATSEMI == 1 + PROGRAMMER_NICNATSEMI +#endif #if CONFIG_GFXNVIDIA == 1 PROGRAMMER_GFXNVIDIA #endif @@ -199,6 +202,24 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICNATSEMI == 1 + { + .name = "nicnatsemi", + .init = nicnatsemi_init, + .shutdown = nicnatsemi_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = nicnatsemi_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicnatsemi_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif #if CONFIG_GFXNVIDIA == 1 { diff --git a/nicnatsemi.c b/nicnatsemi.c new file mode 100644 index 000000000..1878f51dc --- /dev/null +++ b/nicnatsemi.c @@ -0,0 +1,87 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Andrew Morgan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include +#include "flash.h" + +#define PCI_VENDOR_ID_NATSEMI 0x100b + +#define BOOT_ROM_ADDR 0x50 +#define BOOT_ROM_DATA 0x54 + +struct pcidev_status nics_natsemi[] = { + {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, + {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, + {}, +}; + +int nicnatsemi_init(void) +{ + get_io_perms(); + + io_base_addr = pcidev_init(PCI_VENDOR_ID_NATSEMI, PCI_BASE_ADDRESS_0, + nics_natsemi, programmer_param); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + return 0; +} + +int nicnatsemi_shutdown(void) +{ + free(programmer_param); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) +{ + OUTL((uint32_t)addr & 0x0000FFFF, io_base_addr + BOOT_ROM_ADDR); + /* + * The datasheet requires 32 bit accesses to this register, but it seems + * that requirement might only apply if the register is memory mapped. + * Bit 8-31 of this register are apparently don't care, and if this + * register is I/O port mapped 8 bit accesses to the lowest byte of the + * register seem to work fine. Due to that, we ignore the advice in the + * data sheet. + */ + OUTB(val, io_base_addr + BOOT_ROM_DATA); +} + +uint8_t nicnatsemi_chip_readb(const chipaddr addr) +{ + OUTL(((uint32_t)addr & 0x0000FFFF), io_base_addr + BOOT_ROM_ADDR); + /* + * The datasheet requires 32 bit accesses to this register, but it seems + * that requirement might only apply if the register is memory mapped. + * Bit 8-31 of this register are apparently don't care, and if this + * register is I/O port mapped 8 bit accesses to the lowest byte of the + * register seem to work fine. Due to that, we ignore the advice in the + * data sheet. + */ + return INB(io_base_addr + BOOT_ROM_DATA); +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif