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Refactor MCP SPI detection
- Set supported buses based on ISA bridge reg 0x8a - Use MCP55 chipset enable only if LPC is detected - Allow LPC on MCP61 - Eliminate duplicated code where possible Corresponding to flashrom svn r906. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
parent
d8dfc441ed
commit
ce5fad038d
155
chipset_enable.c
155
chipset_enable.c
@ -1054,31 +1054,41 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
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return 0;
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}
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/**
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* The MCP67 code is guesswork based on cleanroom reverse engineering.
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* Due to that, it only reads info and doesn't change any settings.
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* It is assumed that LPC chips need the MCP55 code and SPI chips need the
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* code provided in this function. Until we know for sure, call
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* enable_flash_mcp55 from this function. Warning: enable_flash_mcp55
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* might make SPI flash inaccessible. The same caveat applies to SPI init
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* for LPC flash.
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/* This is a shot in the dark. Even if the code is totally bogus for some
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* chipsets, users will at least start to send in reports.
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*/
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static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
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static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name)
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{
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int result = 0;
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int ret = 0;
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uint8_t byte;
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uint16_t status;
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char *busname;
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uint32_t mcp_spibaraddr;
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void *mcp_spibar;
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struct pci_dev *smbusdev;
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msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
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/* dev is the ISA bridge. No idea what the stuff below does. */
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byte = pci_read_byte(dev, 0x8a);
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msg_pdbg("ISA bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 is "
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"%i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
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msg_pdbg("Guessed flash bus type is %s\n", ((byte >> 5) & 0x3) == 0x2 ?
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"SPI" : "unknown, probably LPC");
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/* Disable the write code for now until we have more info. */
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msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
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"is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
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switch ((byte >> 5) & 0x3) {
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case 0x0:
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buses_supported = CHIP_BUSTYPE_LPC;
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break;
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case 0x2:
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buses_supported = CHIP_BUSTYPE_SPI;
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break;
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default:
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buses_supported = CHIP_BUSTYPE_UNKNOWN;
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break;
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}
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busname = flashbuses_to_text(buses_supported);
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msg_pdbg("Guessed flash bus type is %s\n", busname);
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free(busname);
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/* Force enable SPI and disable LPC? Not a good idea. */
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#if 0
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byte |= (1 << 6);
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byte &= ~(1 << 5);
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@ -1088,8 +1098,15 @@ static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
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/* Look for the SMBus device (SMBus PCI class) */
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smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
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if (!smbusdev) {
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msg_perr("ERROR: SMBus device not found. Aborting.\n");
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exit(1);
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if (buses_supported & CHIP_BUSTYPE_SPI) {
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msg_perr("ERROR: SMBus device not found. Not enabling "
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"SPI.\n");
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buses_supported &= ~CHIP_BUSTYPE_SPI;
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ret = 1;
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} else {
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msg_pinfo("Odd. SMBus device not found.\n");
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}
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goto out_msg;
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}
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msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
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smbusdev->vendor_id, smbusdev->device_id,
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@ -1108,7 +1125,7 @@ static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
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msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);
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/* Accessing a NULL pointer BAR is evil. Don't do it. */
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if (mcp_spibaraddr) {
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if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
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/* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
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mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);
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@ -1125,54 +1142,84 @@ static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
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status, status & 0x1, (status >> 8) & 0x1);
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/* FIXME: Remove the physunmap once the SPI driver exists. */
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physunmap(mcp_spibar, 0x544);
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} else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
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msg_pdbg("Strange. MCP SPI BAR is invalid.\n");
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buses_supported &= ~CHIP_BUSTYPE_SPI;
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ret = 1;
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} else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
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msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
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" doesn't have SPI enabled.\n");
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} else {
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msg_pdbg("Strange. MCP67 SPI BAR is invalid.\n");
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msg_pdbg("MCP SPI is not used.\n");
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}
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out_msg:
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msg_pinfo("Please send the output of \"flashrom -V\" to "
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"flashrom@flashrom.org to help us finish support for your "
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"chipset. Thanks.\n");
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/* Not sure if this is still correct. No docs as usual. */
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result = enable_flash_mcp55(dev, name);
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return ret;
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}
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/**
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* The MCP61/MCP67 code is guesswork based on cleanroom reverse engineering.
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* Due to that, it only reads info and doesn't change any settings.
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* It is assumed that LPC chips need the MCP55 code and SPI chips need the
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* code provided in enable_flash_mcp6x_7x_common. Until we know for sure, call
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* enable_flash_mcp55 from this function only if enable_flash_mcp6x_7x_common
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* indicates the flash chip is LPC. Warning: enable_flash_mcp55
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* might make SPI flash inaccessible. The same caveat applies to SPI init
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* for LPC flash.
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*/
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static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
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{
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int result = 0;
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result = enable_flash_mcp6x_7x_common(dev, name);
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if (result)
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return result;
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/* Not sure if this is correct. No docs as usual. */
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switch (buses_supported) {
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case CHIP_BUSTYPE_LPC:
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result = enable_flash_mcp55(dev, name);
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break;
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case CHIP_BUSTYPE_SPI:
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msg_pinfo("SPI on this chipset is not supported yet.\n");
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buses_supported = CHIP_BUSTYPE_NONE;
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break;
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default:
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msg_pinfo("Something went wrong with bus type detection.\n");
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buses_supported = CHIP_BUSTYPE_NONE;
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break;
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}
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return result;
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}
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/* This is a shot in the dark. Even if the code is totally bogus for some
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* chipsets, users will at least start to send in reports.
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*/
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static int enable_flash_mcp7x(struct pci_dev *dev, const char *name)
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{
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uint8_t byte;
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uint32_t mcp_spibaraddr;
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struct pci_dev *smbusdev;
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int result = 0;
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msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
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result = enable_flash_mcp6x_7x_common(dev, name);
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if (result)
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return result;
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/* dev is the ISA bridge. No idea what the stuff below does. */
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byte = pci_read_byte(dev, 0x8a);
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msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
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"is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
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/* Look for the SMBus device (SMBus PCI class) */
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smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
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if (!smbusdev) {
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msg_perr("ERROR: SMBus device not found. Aborting.\n");
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exit(1);
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/* Not sure if this is correct. No docs as usual. */
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switch (buses_supported) {
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case CHIP_BUSTYPE_LPC:
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msg_pinfo("LPC on this chipset is not supported yet.\n");
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break;
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case CHIP_BUSTYPE_SPI:
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msg_pinfo("SPI on this chipset is not supported yet.\n");
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buses_supported = CHIP_BUSTYPE_NONE;
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break;
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default:
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msg_pinfo("Something went wrong with bus type detection.\n");
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buses_supported = CHIP_BUSTYPE_NONE;
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break;
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}
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msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
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smbusdev->vendor_id, smbusdev->device_id,
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smbusdev->bus, smbusdev->dev, smbusdev->func);
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/* Locate the BAR where the SPI interface lives. */
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mcp_spibaraddr = pci_read_long(smbusdev, 0x74);
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msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);
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msg_pinfo("Please send the output of \"flashrom -V\" to "
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"flashrom@flashrom.org to help us finish support for your "
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"chipset. Thanks.\n");
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return 0;
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return result;
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}
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static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
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@ -1314,10 +1361,10 @@ const struct penable chipset_enables[] = {
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{0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
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{0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
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{0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
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{0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
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{0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
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{0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
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{0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
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{0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
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{0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
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{0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
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{0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
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{0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
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{0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
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{0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
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