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mirror of https://review.coreboot.org/flashrom.git synced 2025-09-18 02:45:23 +02:00

libflashrom,writeprotect: add functions for reading/writing WP configs

New functions are exposed through the libflashrom API for
reading/writing chip's WP settins: `flashrom_wp_{read,write}_cfg()`.

They read/write an opaque `struct flashrom_wp_cfg` instance, which
includes the flash protection range and status register protection mode.

This commit also adds `{read,write}_wp_bits()` helper functions that
read/write chip-specific WP configuration bits.

BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series

Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Nikolai Artemiev
2021-10-21 00:58:12 +11:00
committed by Anastasia Klimchuk
parent 645e5e777a
commit cff87a8488
4 changed files with 363 additions and 0 deletions

View File

@@ -22,8 +22,21 @@
#include <stdbool.h>
#include <stddef.h>
#include "libflashrom.h"
#define MAX_BP_BITS 4
/* Chip protection range: start address and length. */
struct wp_range {
size_t start, len;
};
/* Generic description of a chip's write protection configuration. */
struct flashrom_wp_cfg {
enum flashrom_wp_mode mode;
struct wp_range range;
};
/*
* Description of a chip's write protection configuration.
*
@@ -56,4 +69,12 @@ struct wp_bits {
uint8_t bp[MAX_BP_BITS];
};
struct flashrom_flashctx;
/* Write WP configuration to the chip */
enum flashrom_wp_result wp_write_cfg(struct flashrom_flashctx *, const struct flashrom_wp_cfg *);
/* Read WP configuration from the chip */
enum flashrom_wp_result wp_read_cfg(struct flashrom_wp_cfg *, struct flashrom_flashctx *);
#endif /* !__WRITEPROTECT_H__ */