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ichspi: Add Apollo Lake support
It's almost identical to 100 series PCHs and later. There are some additional FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber
116
ichspi.c
116
ichspi.c
@ -29,6 +29,9 @@
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#include "spi.h"
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#include "ich_descriptors.h"
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/* Apollo Lake */
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#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */
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/* Sunrise Point */
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/* Added HSFS Status bits */
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@ -1564,15 +1567,17 @@ static const char *const access_names[] = {
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static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i)
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{
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const int rwperms_unknown = ARRAY_SIZE(access_names);
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static const char *const region_names[5] = {
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static const char *const region_names[6] = {
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"Flash Descriptor", "BIOS", "Management Engine",
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"Gigabit Ethernet", "Platform Data"
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"Gigabit Ethernet", "Platform Data", "Device Expansion",
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};
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const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
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uint32_t base, limit;
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int rwperms;
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int offset = ICH9_REG_FREG0 + i * 4;
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const int offset = i < 12
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? ICH9_REG_FREG0 + i * 4
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: APL_REG_FREG12 + (i - 12) * 4;
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uint32_t freg = mmio_readl(ich_spibar + offset);
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if (i < 8) {
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@ -1716,8 +1721,10 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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memset(&desc, 0x00, sizeof(struct ich_descriptors));
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/* Moving registers / bits */
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if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
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num_freg = 10;
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switch (ich_generation) {
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_APOLLO_LAKE:
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num_pr = 6; /* Includes GPR0 */
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reg_pr0 = PCH100_REG_FPR0;
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swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
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@ -1727,19 +1734,8 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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hwseq_data.addr_mask = PCH100_FADDR_FLA;
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hwseq_data.only_4k = true;
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hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
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} else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
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num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
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num_pr = 6; /* Includes GPR0 */
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reg_pr0 = PCH100_REG_FPR0;
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swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
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swseq_data.reg_preop = PCH100_REG_PREOP;
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swseq_data.reg_optype = PCH100_REG_OPTYPE;
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swseq_data.reg_opmenu = PCH100_REG_OPMENU;
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hwseq_data.addr_mask = PCH100_FADDR_FLA;
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hwseq_data.only_4k = true;
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hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
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} else {
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num_freg = 5;
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break;
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default:
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num_pr = 5;
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reg_pr0 = ICH9_REG_PR0;
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swseq_data.reg_ssfsc = ICH9_REG_SSFS;
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@ -1749,6 +1745,21 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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hwseq_data.addr_mask = ICH9_FADDR_FLA;
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hwseq_data.only_4k = false;
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hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
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break;
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}
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switch (ich_generation) {
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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num_freg = 10;
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break;
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case CHIPSET_C620_SERIES_LEWISBURG:
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num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
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break;
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case CHIPSET_APOLLO_LAKE:
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num_freg = 16;
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break;
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default:
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num_freg = 5;
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break;
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}
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switch (ich_generation) {
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@ -1834,10 +1845,16 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
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msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
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if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || ich_gen == CHIPSET_C620_SERIES_LEWISBURG) {
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const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
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msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock);
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prettyprint_pch100_reg_dlock(dlock);
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switch (ich_gen) {
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_APOLLO_LAKE:
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tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
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msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
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prettyprint_pch100_reg_dlock(tmp);
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break;
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default:
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break;
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}
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if (desc_valid) {
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@ -1898,37 +1915,51 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
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msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
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swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
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if (ich_generation == CHIPSET_ICH8 && desc_valid) {
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tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
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msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp);
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msg_pdbg("VSCC: ");
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prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
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} else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT &&
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ich_generation != CHIPSET_C620_SERIES_LEWISBURG) {
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if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) {
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if (desc_valid) {
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switch (ich_gen) {
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case CHIPSET_ICH8:
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_BAYTRAIL:
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break;
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default:
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ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
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msg_pdbg("0xA0: 0x%08x (BBAR)\n",
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ichspi_bbar);
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msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
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ich_set_bbar(0);
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break;
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}
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if (desc_valid) {
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if (ich_gen == CHIPSET_ICH8) {
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tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
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msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp);
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msg_pdbg("VSCC: ");
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prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
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} else {
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tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
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msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
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msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp);
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msg_pdbg("LVSCC: ");
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prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
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tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
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msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
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msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp);
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msg_pdbg("UVSCC: ");
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prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
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tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
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msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
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}
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}
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if (desc_valid) {
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switch (ich_gen) {
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case CHIPSET_ICH8:
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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case CHIPSET_APOLLO_LAKE:
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break;
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default:
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tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
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msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp);
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break;
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}
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if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK)
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prettyprint_ich_descriptors(ich_gen, &desc);
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@ -1955,6 +1986,11 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
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ich_spi_mode = ich_hwseq;
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}
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if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) {
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msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n");
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ich_spi_mode = ich_hwseq;
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}
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if (ich_spi_mode == ich_hwseq) {
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if (!desc_valid) {
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msg_perr("Hardware sequencing was requested "
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