openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00
Code Issues Releases Wiki Activity

flashchips,spi25: Replace .wrea_override with FEATURE_4BA_EAR_1716

Browse Source 
There are two competing sets of instructions to access the extended
address register of 4BA SPI chips. Some chips even support both sets.

So far, we assumed the 0xc5/0xc8 instructions by default and allowed
to override the write instructions with the `.wrea_override` field.
This has some disadvantages:

* The additional field is easily overlooked. So when adding a new
  flash chip, one might assume only 0xc5/0xc8 are supported.

* We cannot describe flash chips completely that allow both
  instructions (and some programmers may be picky about which
  instructions can be used).

Therefore, replace the `.wrea_override` field with a feature flag.

Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6d82f24898acd0789203516a7456fd785907bc10
Ticket: https://ticket.coreboot.org/issues/357
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Nico Huber
2022-05-24 15:07:34 +02:00
parent 418916428f
commit d90e2b3e2c
5 changed files with 27 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
include/flash.h
View File

@ -129,10 +129,12 @@ enum write_granularity {
#define FEATURE_4BA_EAR_C5C8 (1 << 13) /**< Regular 3-byte operations can be used by writing the most
significant address byte into an extended address register
(using 0xc5/0xc8 instructions). */
#define FEATURE_4BA_READ (1 << 14) /**< Native 4BA read instruction (0x13) is supported. */
#define FEATURE_4BA_FAST_READ (1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */
#define FEATURE_4BA_WRITE (1 << 16) /**< Native 4BA byte program (0x12) is supported. */
#define FEATURE_4BA_EAR_1716 (1 << 14) /**< Like FEATURE_4BA_EAR_C5C8 but with 0x17/0x16 instructions. */
#define FEATURE_4BA_READ (1 << 15) /**< Native 4BA read instruction (0x13) is supported. */
#define FEATURE_4BA_FAST_READ (1 << 16) /**< Native 4BA fast read instruction (0x0c) is supported. */
#define FEATURE_4BA_WRITE (1 << 17) /**< Native 4BA byte program (0x12) is supported. */
/* 4BA Shorthands */
#define FEATURE_4BA_EAR_ANY (FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_EAR_1716)
#define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE)
#define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
#define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE)
@ -141,13 +143,13 @@ enum write_granularity {
* Most flash chips are erased to ones and programmed to zeros. However, some
* other flash chips, such as the ENE KB9012 internal flash, work the opposite way.
*/
#define FEATURE_ERASED_ZERO (1 << 17)
#define FEATURE_NO_ERASE (1 << 18)
#define FEATURE_ERASED_ZERO (1 << 18)
#define FEATURE_NO_ERASE (1 << 19)
#define FEATURE_WRSR_EXT2 (1 << 19)
#define FEATURE_WRSR2 (1 << 20)
#define FEATURE_WRSR_EXT3 ((1 << 21) | FEATURE_WRSR_EXT2)
#define FEATURE_WRSR3 (1 << 22)
#define FEATURE_WRSR_EXT2 (1 << 20)
#define FEATURE_WRSR2 (1 << 21)
#define FEATURE_WRSR_EXT3 ((1 << 22) | FEATURE_WRSR_EXT2)
#define FEATURE_WRSR3 (1 << 23)
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
@ -277,9 +279,6 @@ struct flashchip {
} voltage;
enum write_granularity gran;
/* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */
uint8_t wrea_override; /**< override opcode for write extended address register */
struct reg_bit_map {
/* Status register protection bit (SRP) */
struct reg_bit_info srp;

2
include/spi.h
View File

@ -175,9 +175,11 @@
/* Write Extended Address Register */
#define JEDEC_WRITE_EXT_ADDR_REG 0xC5
#define ALT_WRITE_EXT_ADDR_REG_17 0x17
/* Read Extended Address Register */
#define JEDEC_READ_EXT_ADDR_REG 0xC8
#define ALT_READ_EXT_ADDR_REG_16 0x16
/* Read the memory */
#define JEDEC_READ 0x03