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mirror of https://review.coreboot.org/flashrom.git synced 2025-08-17 04:14:42 +02:00

Initial Realtek MST i2c_spi support

This spi master allows for programming of a Realtek RTD2142
MST with external SPI flash chip routed via its internal i2c
transport mechanism.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=echo "00000000:0004ffff fw" > layout && \
  flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \
  flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \
  flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \
  flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name

Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
2020-03-26 00:00:41 +11:00
committed by Edward O'Callaghan
parent 3ef0df067b
commit d97f87b00c
6 changed files with 487 additions and 0 deletions

View File

@@ -64,6 +64,7 @@ config_serprog = get_option('config_serprog')
config_usbblaster_spi = get_option('config_usbblaster_spi')
config_stlinkv3_spi = get_option('config_stlinkv3_spi')
config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi')
config_realtek_mst_i2c_spi = get_option('config_realtek_mst_i2c_spi')
cargs = []
deps = []
@@ -288,6 +289,10 @@ if config_lspcon_i2c_spi
srcs += 'lspcon_i2c_spi.c'
cargs += '-DCONFIG_LSPCON_I2C_SPI=1'
endif
if config_realtek_mst_i2c_spi
srcs += 'realtek_mst_i2c_spi.c'
cargs += '-DCONFIG_REALTEK_MST_I2C_SPI=1'
endif
# bitbanging SPI infrastructure
if config_bitbang_spi