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spi25_statusreg.c: add SR3 read/write support

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Adds support for reading and writing the third status register.

Feature flag is not needed because it would never on its own control
whether SR3 access occurs.  If added, it would be in one of three
possible states: wrong, useless or redundant.

Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sergii Dmytruk
2021-12-19 18:37:51 +02:00
committed by Anastasia Klimchuk
parent dcac005071
commit dbbe1588b2
3 changed files with 19 additions and 0 deletions
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8
spi25_statusreg.c
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@ -66,6 +66,11 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
}
msg_cerr("Cannot write SR2: unsupported by chip\n");
return 1;
case STATUS3:
write_cmd[0] = JEDEC_WRSR3;
write_cmd[1] = value;
write_cmd_len = JEDEC_WRSR3_OUTSIZE;
break;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@ -153,6 +158,9 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
}
msg_cerr("Cannot read SR2: unsupported by chip\n");
return 1;
case STATUS3:
read_cmd = JEDEC_RDSR3;
break;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;