openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-10-31 05:10:41 +01:00
Code Issues Releases Wiki Activity

Chipset: Add support for Intel Poulsbo chipset

Browse Source 
Corresponding to flashrom svn r809.

Signed-off-by: Adam Jurkowski <adam.jurkowski@kontron.pl>
Acked-by: Luc Verhaegen <libv@skynet.be>
This commit is contained in:
Adam Jurkowski
2009-12-21 15:30:46 +00:00
committed by Luc Verhaegen
parent b843e2019a
commit e4984102e9
1 changed files with 22 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
chipset_enable.c
View File

@@ -5,6 +5,7 @@
* Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
* Copyright (C) 2009 Kontron Modular Computers GmbH
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -391,6 +392,26 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
return enable_flash_ich(dev, name, 0xdc); return enable_flash_ich(dev, name, 0xdc);
} }
static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
int err;
if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
return err;
old = pci_read_byte(dev, 0xd9);
printf_debug("BIOS Prefetch Enable: %sabled, ",
(old & 1) ? "en" : "dis");
new = old & ~1;
if (new != old)
pci_write_byte(dev, 0xd9, new);
return 0;
}
#define ICH_STRAP_RSVD 0x00 #define ICH_STRAP_RSVD 0x00
#define ICH_STRAP_SPI 0x01 #define ICH_STRAP_SPI 0x01
#define ICH_STRAP_PCI 0x02 #define ICH_STRAP_PCI 0x02
@@ -1155,6 +1176,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
{0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
{0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
{0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo},
{0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
{0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
{0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */