1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

Fix typos

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Change-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Carl-Daniel Hailfinger 2020-01-20 11:22:41 +01:00
parent 67710afe4e
commit e4c2b48f39
2 changed files with 2 additions and 2 deletions

View File

@ -142,7 +142,7 @@ int atavia_init(void)
if (rget_io_perms())
return 1;
dev = pcidev_init(ata_via, PCI_ROM_ADDRESS); /* Acutally no BAR setup needed at all. */
dev = pcidev_init(ata_via, PCI_ROM_ADDRESS); /* Actually no BAR setup needed at all. */
if (!dev)
return 1;

View File

@ -602,7 +602,7 @@
#define PMC_PM49FL004 0x6E
/*
* The Sanyo chip found so far uses SPI, first byte is manufacture code,
* The Sanyo chip found so far uses SPI, first byte is manufacturer code,
* second byte is the device code,
* third byte is a dummy byte.
*/