From e8ce432faafc6794540a2e074af34e5d1fabf138 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 20 Jun 2022 19:32:16 +0200 Subject: [PATCH] flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chips According to their datasheets, ISSI IS25LP256 and IS25WP256 support both 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended address register. Flashrom will use 0xc5 by default if available, so adding the FEATURE_4BA_EAR_1716 flag makes no difference for now (FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA set). It's better to have a comprehensive description of the chips, though, in case somebody wants to use them in the future with a master that restricts available opcodes. Change-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264 Tested-by: build bot (Jenkins) Reviewed-by: Thomas Heijligen --- flashchips.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/flashchips.c b/flashchips.c index b45054c40..5edf6a200 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7469,7 +7469,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_4BA | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -7644,7 +7645,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_4BA | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO,