openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00
Code Issues Releases Wiki Activity

ft2232_spi: Revise comments about output pin states

Browse Source 
The meaning of the variables is easy to misunderstand as some
states are merely implicit: All output pins that are not set
in the `cs_bits` mask will be constantly driven low. This may
be sheer coincidence as all programmers that need additional
pins driven use active-low signals to enable buffers.

While other pins stay low, *all* pins set in the `cs_bits`
mask are supposed to be toggled during SPI transactions.

Also drop some irritating dead code and try to explain things
in a comment.

Change-Id: I2b84ede01759c80f69d5ad17e43783d09ecd1107
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber 2021-06-20 15:59:57 +02:00
parent 2ac057cb39
commit f0915dbc6b
1 changed files with 21 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
ft2232_spi.c
View File

@ -86,14 +86,26 @@ static const struct dev_entry devs_ft2232spi[] = {
#define BITMODE_BITBANG_NORMAL 1
#define BITMODE_BITBANG_SPI 2
/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
* sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
* SCK is bit 0.
* DO is bit 1.
* DI is bit 2.
* CS is bit 3.
/*
* The variables `cs_bits` and `pindir` store the values for the
* "set data bits low byte" MPSSE command that sets the initial
* state and the direction of the I/O pins. `cs_bits` pins default
* to high and will be toggled during SPI transactions. All other
* output pins will be kept low all the time. On exit, all pins
* will be reconfigured as inputs.
*
* The default values (set below in ft2232_spi_init) are used for most devices:
* The pin offsets are as follows:
* TCK/SK is bit 0.
* TDI/DO is bit 1.
* TDO/DI is bit 2.
* TMS/CS is bit 3.
* GPIOL0 is bit 4.
* GPIOL1 is bit 5.
* GPIOL2 is bit 6.
* GPIOL3 is bit 7.
*
* The default values (set below in ft2232_spi_init) are used for
* most devices:
* value: 0x08 CS=high, DI=low, DO=low, SK=low
* dir: 0x0b CS=output, DI=input, DO=output, SK=output
*/
@ -219,7 +231,7 @@ static int ft2232_spi_send_multicommand(const struct flashctx *flash, struct spi
msg_pspew("Assert CS#\n");
buf[i++] = SET_BITS_LOW;
buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */
buf[i++] = 0; /* assert CS# pins, all other output pins stay low */
buf[i++] = spi_data->pindir;
/* WREN, OP(PROGRAM, ERASE), ADDR, DATA */