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ichspi: Change the opcode position for reprogramming on the fly 2->4

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The function for reprogramming on the fly was using the default
configuration O_ST_M25P as a base and the position 2 as the position
to reprogram. Position 2 corresponds to JEDEC_SE which is often useful
for chip erase (when less than whole chip needs to be erased).

This patch changes the default position to reprogram to 4, which
corresponds to JEDEC_REMS. It is used less often, but if it needs to
be used, it will be discovered missing and reprogrammed back.

For erase opcodes, there is usually several of them available. So if
one is missing, erase still can be performed with the remaining ones.
However, this hides the fact that one of available erase opcodes is
missing (it won't be reprogrammed back), and also it gives non-optimal
erase layout.

Context: https://ticket.coreboot.org/issues/556

Change-Id: I6bc855daedf0af2e8de191f23a3512de3ebc3fef
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This commit is contained in:
Anastasia Klimchuk 2024-09-27 18:34:44 +10:00
parent 6c26e9efed
commit f5d1bed6d4
1 changed files with 1 additions and 1 deletions
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2
ichspi.c
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@ -661,7 +661,7 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un
else // we have an invalid case
return SPI_INVALID_LENGTH;
}
int oppos = 2; // use original JEDEC_BE_D8 offset
int oppos = 4; // use the original position of JEDEC_REMS
curopcodes->opcode[oppos].opcode = opcode;
curopcodes->opcode[oppos].spi_type = spi_type;
program_opcodes(curopcodes, 0, ich_generation);