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flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E
Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1428ca25d2
commit
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51
flashchips.c
51
flashchips.c
@ -11258,6 +11258,17 @@ const struct flashchip flashchips[] = {
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {1700, 2000},
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.voltage = {1700, 2000},
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.reg_bits =
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{
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/*
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* There is also a volatile lock register per 64KiB sector, which is not
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* mutually exclusive with BP-based protection.
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*/
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.srp = {STATUS1, 7, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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},
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.decode_range = DECODE_RANGE_SPI25,
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},
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},
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{
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{
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@ -11292,6 +11303,17 @@ const struct flashchip flashchips[] = {
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {2700, 3600},
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.voltage = {2700, 3600},
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.reg_bits =
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{
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/*
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* There is also a volatile lock register per 64KiB sector, which is not
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* mutually exclusive with BP-based protection.
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*/
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.srp = {STATUS1, 7, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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},
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.decode_range = DECODE_RANGE_SPI25,
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},
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},
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{
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{
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@ -11326,6 +11348,17 @@ const struct flashchip flashchips[] = {
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {1700, 2000},
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.voltage = {1700, 2000},
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.reg_bits =
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{
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/*
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* There is also a volatile lock register per 64KiB sector, which is not
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* mutually exclusive with BP-based protection.
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*/
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.srp = {STATUS1, 7, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
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.tb = {STATUS1, 5, RW},
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},
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.decode_range = DECODE_RANGE_SPI25,
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},
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},
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{
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{
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@ -11360,6 +11393,17 @@ const struct flashchip flashchips[] = {
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {2700, 3600},
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.voltage = {2700, 3600},
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.reg_bits =
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{
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/*
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* There is also a volatile lock register per 64KiB sector, which is not
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* mutually exclusive with BP-based protection.
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*/
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.srp = {STATUS1, 7, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
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.tb = {STATUS1, 5, RW},
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},
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.decode_range = DECODE_RANGE_SPI25,
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},
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},
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{
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{
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@ -11999,6 +12043,13 @@ const struct flashchip flashchips[] = {
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
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.voltage = {2700, 3600},
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.voltage = {2700, 3600},
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.reg_bits =
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{
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.srp = {STATUS1, 7, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
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.tb = {STATUS1, 5, RW},
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},
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.decode_range = DECODE_RANGE_SPI25,
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},
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},
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{
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{
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