openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-30 16:33:41 +02:00
Code Issues Releases Wiki Activity

flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E

Browse Source 
Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sergii Dmytruk 2022-07-25 00:28:35 +03:00 committed by Anastasia Klimchuk
parent 1428ca25d2
commit f6b486da14
1 changed files with 51 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
flashchips.c
View File

@ -11258,6 +11258,17 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1700, 2000}, .voltage = {1700, 2000},
.reg_bits =
{
/*
* There is also a volatile lock register per 64KiB sector, which is not
* mutually exclusive with BP-based protection.
*/
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.tb = {STATUS1, 5, RW},
},
.decode_range = DECODE_RANGE_SPI25,
}, },
{ {
@ -11292,6 +11303,17 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600}, .voltage = {2700, 3600},
.reg_bits =
{
/*
* There is also a volatile lock register per 64KiB sector, which is not
* mutually exclusive with BP-based protection.
*/
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.tb = {STATUS1, 5, RW},
},
.decode_range = DECODE_RANGE_SPI25,
}, },
{ {
@ -11326,6 +11348,17 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1700, 2000}, .voltage = {1700, 2000},
.reg_bits =
{
/*
* There is also a volatile lock register per 64KiB sector, which is not
* mutually exclusive with BP-based protection.
*/
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
.tb = {STATUS1, 5, RW},
},
.decode_range = DECODE_RANGE_SPI25,
}, },
{ {
@ -11360,6 +11393,17 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600}, .voltage = {2700, 3600},
.reg_bits =
{
/*
* There is also a volatile lock register per 64KiB sector, which is not
* mutually exclusive with BP-based protection.
*/
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
.tb = {STATUS1, 5, RW},
},
.decode_range = DECODE_RANGE_SPI25,
}, },
{ {
@ -11999,6 +12043,13 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600}, .voltage = {2700, 3600},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
.tb = {STATUS1, 5, RW},
},
.decode_range = DECODE_RANGE_SPI25,
}, },
{ {