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spi25_statusreg: Allow WRSR_EXT for Status Register 3

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Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to
write more than 2 registers. So align SR2 and SR3 support: The current
FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3
is added. Also, WRSR3 needs a separate flag now.

Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.

Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Nico Huber
2022-05-28 16:48:26 +02:00
parent 7db2baa77d
commit f6d702e2d0
6 changed files with 83 additions and 38 deletions
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4
include/flash.h
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@ -143,8 +143,10 @@ enum write_granularity {
#define FEATURE_ERASED_ZERO (1 << 17)
#define FEATURE_NO_ERASE (1 << 18)
#define FEATURE_WRSR_EXT (1 << 19)
#define FEATURE_WRSR_EXT2 (1 << 19)
#define FEATURE_WRSR2 (1 << 20)
#define FEATURE_WRSR_EXT3 ((1 << 21) | FEATURE_WRSR_EXT2)
#define FEATURE_WRSR3 (1 << 22)
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)

1
include/spi.h
View File

@ -156,7 +156,6 @@
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02
#define JEDEC_WRSR_INSIZE 0x00
#define JEDEC_WRSR_EXT_OUTSIZE 0x03
/* Write Status Register 2 */
#define JEDEC_WRSR2 0x31