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Code Issues Releases Wiki Activity

ichspi: Merge spi_master implementations for Intel ich

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There seems no problem to use ich_spi_probe_opcode() for
spi_master::probe_opcode() on ich7, so we may merge former
spi_master_ich7 and spi_master_ich9 into spi_master_ich, for both
init_ich7_spi() and init_ich_default().

Change-Id: I6a65c97e910622a55da7cef8a10de3af6a99c9e8
Signed-off-by: persmule <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84593
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This commit is contained in:
persmule 2024-09-30 15:19:01 +08:00 committed by Anastasia Klimchuk
parent 0332d5e3ad
commit f80caddca0
1 changed files with 3 additions and 14 deletions
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17
ichspi.c
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@ -1991,18 +1991,7 @@ static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_pr
msg_gspew("resulted in 0x%08"PRIx32".\n", mmio_readl(addr)); msg_gspew("resulted in 0x%08"PRIx32".\n", mmio_readl(addr));
} }
static const struct spi_master spi_master_ich7 = { static const struct spi_master spi_master_ich = {
.max_data_read = 64,
.max_data_write = 64,
.command = ich_spi_send_command,
.multicommand = ich_spi_send_multicommand,
.map_flash_region = physmap,
.unmap_flash_region = physunmap,
.read = default_spi_read,
.write_256 = default_spi_write_256,
};
static const struct spi_master spi_master_ich9 = {
.max_data_read = 64, .max_data_read = 64,
.max_data_write = 64, .max_data_write = 64,
.command = ich_spi_send_command, .command = ich_spi_send_command,
@ -2054,7 +2043,7 @@ static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen)
} }
ich_init_opcodes(ich_gen); ich_init_opcodes(ich_gen);
ich_set_bbar(0, ich_gen); ich_set_bbar(0, ich_gen);
register_spi_master(&spi_master_ich7, NULL); register_spi_master(&spi_master_ich, NULL);
return 0; return 0;
} }
@ -2420,7 +2409,7 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
memcpy(opaque_hwseq_data, &hwseq_data, sizeof(*opaque_hwseq_data)); memcpy(opaque_hwseq_data, &hwseq_data, sizeof(*opaque_hwseq_data));
register_opaque_master(&opaque_master_ich_hwseq, opaque_hwseq_data); register_opaque_master(&opaque_master_ich_hwseq, opaque_hwseq_data);
} else { } else {
register_spi_master(&spi_master_ich9, NULL); register_spi_master(&spi_master_ich, NULL);
} }
return 0; return 0;