mirror of
https://review.coreboot.org/flashrom.git
synced 2025-07-02 14:33:18 +02:00
Add detailed status register printing and unlocking for all ATMEL AT25* chips
Add support for Atmel AT25DF081A and AT25DQ161. Some chips require EWSR before WRSR, others require WREN before WRSR, and some support both variants. Add feature_bits to select the correct SPI command, and default to EWSR. Corresponding to flashrom svn r1115. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Steven Rosario Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Carl-Daniel Hailfinger
326
spi25.c
326
spi25.c
@ -312,7 +312,16 @@ uint8_t spi_read_status_register(void)
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}
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/* Prettyprint the status register. Common definitions. */
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void spi_prettyprint_status_register_common(uint8_t status)
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static void spi_prettyprint_status_register_welwip(uint8_t status)
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{
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msg_cdbg("Chip status register: Write Enable Latch (WEL) is "
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"%sset\n", (status & (1 << 1)) ? "" : "not ");
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msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is "
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"%sset\n", (status & (1 << 0)) ? "" : "not ");
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}
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/* Prettyprint the status register. Common definitions. */
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static void spi_prettyprint_status_register_common(uint8_t status)
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{
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msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
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"%sset\n", (status & (1 << 5)) ? "" : "not ");
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@ -322,10 +331,7 @@ void spi_prettyprint_status_register_common(uint8_t status)
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"%sset\n", (status & (1 << 3)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
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"%sset\n", (status & (1 << 2)) ? "" : "not ");
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msg_cdbg("Chip status register: Write Enable Latch (WEL) is "
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"%sset\n", (status & (1 << 1)) ? "" : "not ");
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msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is "
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"%sset\n", (status & (1 << 0)) ? "" : "not ");
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spi_prettyprint_status_register_welwip(status);
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}
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/* Prettyprint the status register. Works for
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@ -338,6 +344,121 @@ void spi_prettyprint_status_register_amic_a25l(uint8_t status)
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spi_prettyprint_status_register_common(status);
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}
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/* Prettyprint the status register. Common definitions. */
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static void spi_prettyprint_status_register_at25_srplepewpp(uint8_t status)
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{
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msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) "
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"is %sset\n", (status & (1 << 7)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 6 "
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"is %sset\n", (status & (1 << 6)) ? "" : "not ");
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msg_cdbg("Chip status register: Erase/Program Error (EPE) "
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"is %sset\n", (status & (1 << 5)) ? "" : "not ");
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msg_cdbg("Chip status register: WP# pin (WPP) "
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"is %sactive\n", (status & (1 << 4)) ? "not " : "");
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}
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int spi_prettyprint_status_register_at25df(struct flashchip *flash)
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{
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uint8_t status;
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status = spi_read_status_register();
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msg_cdbg("Chip status register is %02x\n", status);
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spi_prettyprint_status_register_at25_srplepewpp(status);
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msg_cdbg("Chip status register: Software Protection Status (SWP): ");
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switch (status & (3 << 2)) {
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case 0x0 << 2:
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msg_cdbg("no sectors are protected\n");
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break;
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case 0x1 << 2:
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msg_cdbg("some sectors are protected\n");
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/* FIXME: Read individual Sector Protection Registers. */
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break;
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case 0x3 << 2:
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msg_cdbg("all sectors are protected\n");
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break;
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default:
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msg_cdbg("reserved for future use\n");
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break;
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}
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash)
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{
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/* FIXME: We should check the security lockdown. */
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msg_cdbg("Ignoring security lockdown (if present)\n");
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msg_cdbg("Ignoring status register byte 2\n");
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return spi_prettyprint_status_register_at25df(flash);
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}
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int spi_prettyprint_status_register_at25f(struct flashchip *flash)
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{
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uint8_t status;
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status = spi_read_status_register();
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msg_cdbg("Chip status register is %02x\n", status);
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spi_prettyprint_status_register_at25_srplepewpp(status);
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msg_cdbg("Chip status register: Bit 3 "
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"is %sset\n", (status & (1 << 3)) ? "" : "not ");
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msg_cdbg("Chip status register: Block Protect 0 (BP0) is "
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"%sset, %s sectors are protected\n",
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(status & (1 << 2)) ? "" : "not ",
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(status & (1 << 2)) ? "all" : "no");
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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int spi_prettyprint_status_register_at25fs010(struct flashchip *flash)
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{
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uint8_t status;
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status = spi_read_status_register();
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msg_cdbg("Chip status register is %02x\n", status);
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msg_cdbg("Chip status register: Status Register Write Protect (WPEN) "
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"is %sset\n", (status & (1 << 7)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is "
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"%sset\n", (status & (1 << 6)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
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"%sset\n", (status & (1 << 5)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 4 is "
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"%sset\n", (status & (1 << 4)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
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"%sset\n", (status & (1 << 3)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
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"%sset\n", (status & (1 << 2)) ? "" : "not ");
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/* FIXME: Pretty-print detailed sector protection status. */
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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int spi_prettyprint_status_register_at25fs040(struct flashchip *flash)
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{
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uint8_t status;
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status = spi_read_status_register();
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msg_cdbg("Chip status register is %02x\n", status);
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msg_cdbg("Chip status register: Status Register Write Protect (WPEN) "
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"is %sset\n", (status & (1 << 7)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is "
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"%sset\n", (status & (1 << 6)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
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"%sset\n", (status & (1 << 5)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
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"%sset\n", (status & (1 << 4)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
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"%sset\n", (status & (1 << 3)) ? "" : "not ");
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msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
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"%sset\n", (status & (1 << 2)) ? "" : "not ");
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/* FIXME: Pretty-print detailed sector protection status. */
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spi_prettyprint_status_register_welwip(status);
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return 0;
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}
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/* Prettyprint the status register. Works for
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* ST M25P series
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* MX MX25L series
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@ -732,12 +853,12 @@ int spi_write_status_enable(void)
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* This is according the SST25VF016 datasheet, who knows it is more
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* generic that this...
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*/
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int spi_write_status_register(int status)
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static int spi_write_status_register_ewsr(struct flashchip *flash, int status)
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{
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int result;
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struct spi_command cmds[] = {
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{
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/* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
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/* WRSR requires either EWSR or WREN depending on chip type. */
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.writecnt = JEDEC_EWSR_OUTSIZE,
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.writearr = (const unsigned char[]){ JEDEC_EWSR },
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.readcnt = 0,
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@ -759,9 +880,59 @@ int spi_write_status_register(int status)
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msg_cerr("%s failed during command execution\n",
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__func__);
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}
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/* WRSR performs a self-timed erase before the changes take effect. */
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programmer_delay(100 * 1000);
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return result;
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}
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static int spi_write_status_register_wren(struct flashchip *flash, int status)
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{
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int result;
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struct spi_command cmds[] = {
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{
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/* WRSR requires either EWSR or WREN depending on chip type. */
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.writecnt = JEDEC_WREN_OUTSIZE,
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.writearr = (const unsigned char[]){ JEDEC_WREN },
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.readcnt = 0,
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.readarr = NULL,
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}, {
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.writecnt = JEDEC_WRSR_OUTSIZE,
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.writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
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.readcnt = 0,
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.readarr = NULL,
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}, {
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.writecnt = 0,
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.writearr = NULL,
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.readcnt = 0,
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.readarr = NULL,
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}};
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result = spi_send_multicommand(cmds);
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if (result) {
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msg_cerr("%s failed during command execution\n",
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__func__);
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}
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/* WRSR performs a self-timed erase before the changes take effect. */
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programmer_delay(100 * 1000);
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return result;
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}
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static int spi_write_status_register(struct flashchip *flash, int status)
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{
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int ret = 1;
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if (!(flash->feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {
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msg_cdbg("Missing status register write definition, assuming "
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"EWSR is needed\n");
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flash->feature_bits |= FEATURE_WRSR_EWSR;
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}
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if (flash->feature_bits & FEATURE_WRSR_WREN)
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ret = spi_write_status_register_wren(flash, status);
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if (ret && (flash->feature_bits & FEATURE_WRSR_EWSR))
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ret = spi_write_status_register_ewsr(flash, status);
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return ret;
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}
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int spi_byte_program(int addr, uint8_t databyte)
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{
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int result;
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@ -844,26 +1015,153 @@ int spi_nbyte_program(int addr, uint8_t *bytes, int len)
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return result;
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}
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/* A generic brute-force block protection disable works like this:
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* Write 0x00 to the status register. Check if any locks are still set (that
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* part is chip specific). Repeat once.
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*/
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int spi_disable_blockprotect(struct flashchip *flash)
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{
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uint8_t status;
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int result;
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status = spi_read_status_register();
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/* If there is block protection in effect, unprotect it first. */
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/* If block protection is disabled, stop here. */
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if ((status & 0x3c) == 0)
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return 0;
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msg_cdbg("Some block protection in effect, disabling\n");
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result = spi_write_status_register(flash, status & ~0x3c);
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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status = spi_read_status_register();
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if ((status & 0x3c) != 0) {
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msg_cdbg("Some block protection in effect, disabling\n");
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result = spi_write_status_register(status & ~0x3c);
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msg_cerr("Block protection could not be disabled!\n");
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return 1;
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}
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return 0;
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}
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int spi_disable_blockprotect_at25df(struct flashchip *flash)
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{
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uint8_t status;
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int result;
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status = spi_read_status_register();
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/* If block protection is disabled, stop here. */
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if ((status & (3 << 2)) == 0)
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return 0;
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msg_cdbg("Some block protection in effect, disabling\n");
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if (status & (1 << 7)) {
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msg_cdbg("Need to disable Sector Protection Register Lock\n");
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if ((status & (1 << 4)) == 0) {
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msg_cerr("WP# pin is active, disabling "
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"write protection is impossible.\n");
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return 1;
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}
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/* All bits except bit 7 (SPRL) are readonly. */
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result = spi_write_status_register(flash, status & ~(1 << 7));
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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status = spi_read_status_register();
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if ((status & 0x3c) != 0) {
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msg_cerr("Block protection could not be disabled!\n");
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return 1;
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}
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/* Global unprotect. Make sure to mask SPRL as well. */
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result = spi_write_status_register(flash, status & ~0xbc);
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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status = spi_read_status_register();
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if ((status & (3 << 2)) != 0) {
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msg_cerr("Block protection could not be disabled!\n");
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return 1;
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}
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return 0;
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}
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int spi_disable_blockprotect_at25df_sec(struct flashchip *flash)
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{
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/* FIXME: We should check the security lockdown. */
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msg_cinfo("Ignoring security lockdown (if present)\n");
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return spi_disable_blockprotect_at25df(flash);
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}
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int spi_disable_blockprotect_at25f(struct flashchip *flash)
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{
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/* spi_disable_blockprotect_at25df is not really the right way to do
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* this, but the side effects of said function work here as well.
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*/
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return spi_disable_blockprotect_at25df(flash);
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}
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int spi_disable_blockprotect_at25fs010(struct flashchip *flash)
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{
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uint8_t status;
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int result;
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status = spi_read_status_register();
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/* If block protection is disabled, stop here. */
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if ((status & 0x6c) == 0)
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return 0;
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msg_cdbg("Some block protection in effect, disabling\n");
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if (status & (1 << 7)) {
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msg_cdbg("Need to disable Status Register Write Protect\n");
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/* Clear bit 7 (WPEN). */
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result = spi_write_status_register(flash, status & ~(1 << 7));
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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}
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/* Global unprotect. Make sure to mask WPEN as well. */
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result = spi_write_status_register(flash, status & ~0xec);
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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status = spi_read_status_register();
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if ((status & 0x6c) != 0) {
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msg_cerr("Block protection could not be disabled!\n");
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return 1;
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}
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return 0;
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}
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int spi_disable_blockprotect_at25fs040(struct flashchip *flash)
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{
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uint8_t status;
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int result;
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status = spi_read_status_register();
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/* If block protection is disabled, stop here. */
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if ((status & 0x7c) == 0)
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return 0;
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msg_cdbg("Some block protection in effect, disabling\n");
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if (status & (1 << 7)) {
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msg_cdbg("Need to disable Status Register Write Protect\n");
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/* Clear bit 7 (WPEN). */
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result = spi_write_status_register(flash, status & ~(1 << 7));
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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}
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/* Global unprotect. Make sure to mask WPEN as well. */
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result = spi_write_status_register(flash, status & ~0xfc);
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if (result) {
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msg_cerr("spi_write_status_register failed\n");
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return result;
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}
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status = spi_read_status_register();
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if ((status & 0x7c) != 0) {
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msg_cerr("Block protection could not be disabled!\n");
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return 1;
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}
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return 0;
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}
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