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flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L

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These chips seem to be rather regular, supporting 2.7V..3.6V, the
common erase block sizes 4KiB, 32KiB, 64KiB and the usual block-
protection bits.

Status/configuration register naming differs from other vendors,
though. These chips have 2 status registers plus 3 configuration
registers. Configuration registers 1 & 2 match status registers
2 & 3 of what we are used from other vendors. Read opcodes match
too, however writes are always done through the WRSR instruction
which can write up to 4 bytes (SR1, CR1, CR2, CR3).

S25FL256L supports native 4BA commands and entering a 4BA mode.
However, it uses an unusual opcode (0x53) for the 32KiB 4BA block
erase.

Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2022-05-28 14:26:06 +02:00
parent f6d702e2d0
commit fe47c15b99
4 changed files with 135 additions and 0 deletions
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9
spi25.c
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@ -588,6 +588,13 @@ int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int b
return spi_write_cmd(flash, 0x21, true, addr, NULL, 0, 10 * 1000);
}
/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
int spi_block_erase_53(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
{
/* This usually takes 100-4000ms, so wait in 100ms steps. */
return spi_write_cmd(flash, 0x53, true, addr, NULL, 0, 100 * 1000);
}
/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
{
@ -617,6 +624,8 @@ erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)
return &spi_block_erase_50;
case 0x52:
return &spi_block_erase_52;
case 0x53:
return &spi_block_erase_53;
case 0x5c:
return &spi_block_erase_5c;
case 0x60: