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flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L
These chips seem to be rather regular, supporting 2.7V..3.6V, the common erase block sizes 4KiB, 32KiB, 64KiB and the usual block- protection bits. Status/configuration register naming differs from other vendors, though. These chips have 2 status registers plus 3 configuration registers. Configuration registers 1 & 2 match status registers 2 & 3 of what we are used from other vendors. Read opcodes match too, however writes are always done through the WRSR instruction which can write up to 4 bytes (SR1, CR1, CR2, CR3). S25FL256L supports native 4BA commands and entering a 4BA mode. However, it uses an unusual opcode (0x53) for the 32KiB 4BA block erase. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
parent
f6d702e2d0
commit
fe47c15b99
123
flashchips.c
123
flashchips.c
@ -16182,6 +16182,63 @@ const struct flashchip flashchips[] = {
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.voltage = {2700, 3600},
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},
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{
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.vendor = "Spansion",
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.name = "S25FL128L",
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.bustype = BUS_SPI,
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.manufacture_id = SPANSION_ID,
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.model_id = SPANSION_S25FL128L,
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.total_size = 16384,
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.page_size = 256,
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/* 4 x 256B Security Region (OTP) */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP,
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.tested = TEST_UNTESTED,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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.block_erasers =
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{
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{
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.eraseblocks = { {4 * 1024, 4096} },
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.block_erase = spi_block_erase_20,
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}, {
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.eraseblocks = { {32 * 1024, 512} },
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.block_erase = spi_block_erase_52,
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}, {
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.eraseblocks = { {64 * 1024, 256} },
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.block_erase = spi_block_erase_d8,
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}, {
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.eraseblocks = { {16384 * 1024, 1} },
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.block_erase = spi_block_erase_60,
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}, {
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.eraseblocks = { {16384 * 1024, 1} },
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.block_erase = spi_block_erase_c7,
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}
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},
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.printlock = spi_prettyprint_status_register_bp2_srwd,
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.unlock = spi_disable_blockprotect_bp2_srwd,
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.write = spi_chip_write_256,
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.read = spi_chip_read, /* Fast read (0x0B) supported */
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.voltage = {2700, 3600},
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.reg_bits =
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{
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/*
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* Note: This chip has a read-only Status Register 2 that is not
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* counted here. Registers are mapped as follows:
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* STATUS1 ... Status Register 1
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* STATUS2 ... Configuration Register 1
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* STATUS3 ... Configuration Register 2
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*/
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
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.tb = {STATUS1, 5, RW},
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.sec = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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.wps = {STATUS3, 2, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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.vendor = "Spansion",
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.name = "S25FL128P......0", /* uniform 64 kB sectors */
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@ -16609,6 +16666,72 @@ const struct flashchip flashchips[] = {
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.voltage = {2700, 3600},
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},
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{
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.vendor = "Spansion",
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.name = "S25FL256L",
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.bustype = BUS_SPI,
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.manufacture_id = SPANSION_ID,
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.model_id = SPANSION_S25FL256L,
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.total_size = 32768,
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.page_size = 256,
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/* 4 x 256B Security Region (OTP) */
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.feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP |
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FEATURE_4BA_ENTER | FEATURE_4BA_NATIVE,
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.tested = TEST_UNTESTED,
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.probe = probe_spi_rdid,
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.probe_timing = TIMING_ZERO,
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.block_erasers =
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{
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{
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.eraseblocks = { {4 * 1024, 8192} },
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.block_erase = spi_block_erase_21,
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}, {
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.eraseblocks = { {4 * 1024, 8192} },
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.block_erase = spi_block_erase_20,
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}, {
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.eraseblocks = { {32 * 1024, 1024} },
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.block_erase = spi_block_erase_53,
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}, {
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.eraseblocks = { {32 * 1024, 1024} },
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.block_erase = spi_block_erase_52,
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}, {
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.eraseblocks = { {64 * 1024, 512} },
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.block_erase = spi_block_erase_dc,
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}, {
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.eraseblocks = { {64 * 1024, 512} },
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.block_erase = spi_block_erase_d8,
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}, {
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.eraseblocks = { {32768 * 1024, 1} },
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.block_erase = spi_block_erase_60,
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}, {
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.eraseblocks = { {32768 * 1024, 1} },
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.block_erase = spi_block_erase_c7,
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}
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},
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.printlock = spi_prettyprint_status_register_bp3_srwd,
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.unlock = spi_disable_blockprotect_bp3_srwd,
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.write = spi_chip_write_256,
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.read = spi_chip_read, /* Fast read (0x0B) supported */
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.voltage = {2700, 3600},
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.reg_bits =
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{
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/*
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* Note: This chip has a read-only Status Register 2 that is not
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* counted here. Registers are mapped as follows:
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* STATUS1 ... Status Register 1
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* STATUS2 ... Configuration Register 1
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* STATUS3 ... Configuration Register 2
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*/
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.srp = {STATUS1, 7, RW},
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.srl = {STATUS2, 0, RW},
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.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
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.tb = {STATUS1, 6, RW},
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.cmp = {STATUS2, 6, RW},
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.wps = {STATUS3, 2, RW},
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},
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.decode_range = decode_range_spi25,
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},
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{
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.vendor = "Spansion",
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.name = "S25FL256S Large Sectors",
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@ -41,6 +41,7 @@ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int b
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int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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int spi_block_erase_53(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
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@ -668,6 +668,8 @@
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#define SPANSION_S25FL116K 0x4015
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#define SPANSION_S25FL132K 0x4016
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#define SPANSION_S25FL164K 0x4017
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#define SPANSION_S25FL128L 0x6018
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#define SPANSION_S25FL256L 0x6019
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#define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */
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#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */
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#define SPANSION_S25FS256S_L 0x02190081 /* Large sectors. */
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9
spi25.c
9
spi25.c
@ -588,6 +588,13 @@ int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int b
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return spi_write_cmd(flash, 0x21, true, addr, NULL, 0, 10 * 1000);
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}
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/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
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int spi_block_erase_53(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
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{
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/* This usually takes 100-4000ms, so wait in 100ms steps. */
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return spi_write_cmd(flash, 0x53, true, addr, NULL, 0, 100 * 1000);
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}
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/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
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int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
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{
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@ -617,6 +624,8 @@ erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)
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return &spi_block_erase_50;
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case 0x52:
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return &spi_block_erase_52;
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case 0x53:
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return &spi_block_erase_53;
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case 0x5c:
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return &spi_block_erase_5c;
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case 0x60:
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