If none of "Full name" or "Display name" is set for a Gerrit account,
code reviews emails are sent from "Name of user not set" instead of
a user name. It is worth clarifying explicitly in the docs.
Change-Id: I69b6f5c1c56a2798dd156582cb5fa246b2396ab3
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/79250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Stanislav Ponomarev <me@stasponomarev.com>
CONFIG_INTERNAL depends on raw mem access resulting in the following
build failure on sh4 since version 1.3.0:
/home/thomas/autobuild/instance-3/output-1/per-package/flashrom/host/bin/../lib/gcc/sh4a-buildroot-linux-gnu/12.3.0/../../../../sh4a-buildroot-linux-gnu/bin/ld: libflashrom.a(internal.o): in function `internal_chip_readn':
internal.c:(.text+0x8): undefined reference to `mmio_readn'
Fixes the build raised by buildroot autobuilders with the following
options:
- CONFIG_FT2232_SPI=no
- CONFIG_USBBLASTER_SPI=no
- CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=yes
- CONFIG_ENABLE_LIBPCI_PROGRAMMERS=yes
Here is the target information:
C compiler found: sh4a-buildroot-linux-gnu-gcc.br_real (Buildroot 2022.08-rc1-5515-gf1a47904b63) 12.3.0
Target arch: sh
Target OS: Linux
Target endian: little
Full build log:
- http://autobuild.buildroot.org/results/f74a9d315fb519f284428234713f43fcf4e35fd0
Change-Id: I7610f5f7cc5b114ffa90d5752155acc8b6b7c9f7
Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Use build system to check header presence:
* getopt.h (from include/cli_classic.h)
* pciutils/pci.h (from include/platform/pci.h)
Tested with <getopt.h> and <pci/pci.h> using GNU Make 4.1, 4.2.1, 4.4.1
and Meson 0.56.0, 1.2.1 against GCC 13.2.1 and GCC 5.5-, 7.3-compatible
(EDG 4.14-, 5.1-based) on openSuSE Tumbleweed and a custom LFS distro.
Change-Id: Ic544963ffd29626ae0a21bdddb1c78850cc43ec6
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77089
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During the development of an esp32 serprog-compatible SPI programmer,
and implementation of the TCP over Wi-Fi for serprog,
I discovered that sp_flush_incoming() silently fails
if the underlying sp_fd descriptor is a TCP socket.
This patch adds a check for this case - tcflush returns ENOTTY,
meaning tcflush is not supported for not terminal objects,
in this case a fallback serialport_read_nonblock loop is used.
TESTED=esp32-serprog, TCP-over-WiFi mode, ~90% connection attempts fail to synchronize without patch; no synchronization issues with patch applied.
Signed-off-by: Stanislav Ponomarev <me@stasponomarev.com>
Change-Id: I9724a2fcd4a41dede2c15f83877efa6c3b0b7fae
Reviewed-on: https://review.coreboot.org/c/flashrom/+/79112
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C
does. So we need to split the existing GD25Q127C/GD25Q128C into two
separated entries. We also introduce the new flashchip Q128E and merge
it into Q127C.
Datasheets:
Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00480-GD25Q128E-Rev1.2.pdf
Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf
Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf
Q128E and Q127C/Q128C have compatible main functions, their differences
are:
* Q128E uses 55 nm process, while Q127C/Q128C use 65nm
* Q128E/Q127C does not support QPI
* Q128E/Q127C have OTP: 3072B, while Q128C are 1536B
* Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are
104MHZ
So we decided to merge Q128E into Q127C.
We also tested that Q128E could pass flashrom_tester while probing it as
127C/128C, so the main functionalities are compatible.
Change the chip name from GD25Q127C/GD25Q128C to two entries
GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate.
Chip revision history:
- The 'GD25Q127C/GD25Q128C' definition was added in
`commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
later renamed to 'GD25Q127C/GD25Q128C'
BUG=b:304863141, b:293545382
BRANCH=none
TEST=flashrom_tester with flashrom binary could pass with Q128E,
which contains probe, read, write, erase, and write protect
Signed-off-by: Hsuan Ting Chen <roccochen@google.com>
Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Other chips (at least Winbond) will benefit from this change.
Also, drop the FIXME comment, as it can be misleading. The
"pretty print" functions should only display values from the
Status Register, so using an inappropriate function might only
confuse user.
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Change-Id: I7169a2312698343e1065cdca91a3985e00cb3804
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
The test checks that algorithm for erase functions selection
works and there are no regressions.
Specifically, test contains an array of test cases. Each case
initialises a given initial state of the memory for the mock chip,
and layout regions on the chip, and then performs erase and write
operations.
At the end of operation, test asserts the following:
- the state of mock chip memory is as expected, i.e. properly erased
or written
- erase blocks are invoked in expected order and expected number
of them
- chip operation (erase or write) returned 0.
Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Erasefn was invoked over the same block of memory twice.
This patch removes the second redundant invokation. It was
accidentally introduced during earlier refactoring of the code.
Change-Id: I92351eba0fd29114ce98b4a839358e92d176af28
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77747
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Some devices such as the GSC knows how it is wired to AP and EC flash
chips, and can be told which specific device to talk to. Other devices
such as Servo Micro and HyperDebug are generic, and do not know how they
are wired, the caller is responsible for first configure the appropriate
MUXes or buffers, and then tell the debugger which port to use (Servo
Micro has just one SPI port, HyperDebug is the first that has multiple).
The Raiden protocol allows both the cases of USB devices knowing their
wiring and not.
If I were to declare the protocol in Rust, this is how the information
of the Raiden protocol "enable request" would be encoded:
```
enum {
EnableGeneric(u8),
EnableAp,
EnableEc,
...
}
```
The first label `EnableGeneric(u8)` is to be used with HyperDebug that
does not know how its ports are wired, and allow access by index.
The other labels `EnableAp` and `EnableEc` are to be used with the GSC.
The actual transmission of the enum above uses the bRequest and low byte
of wValue of a USB control request, but that is a detail and not
conceptually important.
Until now, `-p raiden_debug_spi:target=AP` or `...:target=EC` could be
used to make flashrom use `EnableAp` or `EnableEc`, and if neither was
given, it would default to `EnableGeneric`, which now that wValue is
used means `EnableGeneric(0)`.
I find it rather straight-forward, that `-p raiden_debug_spi:target=1`,
`...:target=2`, etc. should translate to `EnableGeneric(1)`, etc.
This patchset achieves this, by adding a second 16-bit parameter value,
next to request_enable.
I have tested that flashrom can detect the same Winbond flash chip
"W25Q128.V..M" with two different Raiden USB devices as below.
TEST=flashrom -p raiden_debug_spi:serial=0701B044-91AC3132,target=AP
TEST=flashrom -p raiden_debug_spi:serial=205635783236,target=1
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I03bf4f3210186fb5937b42e298761907b03e08b7
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Running tests is one of the regular things to do in dev process,
same as compile, so it should be highlighted in the TLDR section
of the document.
The patch adds test command to TLDR version in README file, and
in dedicated meson instructions doc.
Change-Id: I67d5f4decdac15e6a72f4372135dab7d44396594
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78689
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Clean commit 51e1d0e4b7670e5822560acc724a6a8dd00b6af4
'Add support for Intel Emmitsburg PCH' which broke
CHIPSET_5_SERIES_IBEX_PEAK detection and which assumes C740 is the same
as C620, while its more a close relative to Intel's H570 PCH.
Based on Intel SPI Programming Guide #619386.
Test: Run on Intel ArcherCity CRB with Intel's C741 PCH
using the 'internal' programmer.
Test: Run on BMC and accessed the SPI flash chip over
'linux_mtd' programmer.
Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78186
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code uses "%-4s" to print the master names and thus assumes that
all names have 4 characters or less. Convert "unknown" to "DevE",
short for Device Expansion in order to properly display the table.
Test: Run flashrom -p internal -VV
Change-Id: I0d10e2771c7a27c1a73ed53a33e68a04eb9e1e00
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78301
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow nm, the number of flash masters, to be equal to
ARRAY_SIZE(master_names). The previous logic was probably overlooked
when ich_number_of_masters() was introduced. The loop below makes sure
that it doesn't access the master_names array out of bounds.
Change-Id: Ib9276a6c29952487db6e60fb583942c0f24cd6ef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
As a starting point, copying coreboot's one in the absence
of our own.
coreboot's CoC exists for some time and is known to work, so
it's a good starting point. We can iterate on this and make
upgrades and amendments that make sense for flashrom community.
Meanwhile we can share code of conduct with coreboot. We
do have the same servers and infrastructure anyway.
Change-Id: Icd82ba79687da3a2698d84f5cbfe824fbab0c426
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updated the information that WP is included in the v1.3 release,
and added links to dev guidelines on how to build from head
(instead of inlining the instructions).
Change-Id: I223f1aa5f4531b28b04bcfcecd9becfa7899c3d9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78113
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Example of commit message was formatted with code-block directive
which has language argument required or optional depending on the
sphinx version. Replace code-block with simpler literal block
which never has arguments, and also since the text formatted is
not actually a code.
Change-Id: If0bc8327e973d9bc9a93eea38c83bfab412fb8f4
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
XM25QH80B has the same ID as M45PE80, but has more features.
Tested with CH341A.
Change-Id: Ib51225426d8d1a381d45af3574e5ba2bf02837aa
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63516
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since doc/meson.build uses `str.substring()` introduced in Meson 0.56.0,
the root meson.build should be updated from 0.53.0.
Change-Id: I53c6c42c27a58734742e3dce3cdbde4c65b89a90
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77779
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Don't unlock using WP for read/verify operations because WP will only
disable write locks. Most chips don't have read locks anyway, but some
do, so we still call the chip's unlock function for read/verify
operations.
Unconditionally unlocking using WP slows down flashrom significantly
with some programmers, particularly linux_mtd due to inefficiency in the
current kernel MTD interface.
BUG=b:283779258
BRANCH=none
TEST=`ninja test`
TEST=`flashrom -{r,w,E,v}` on strongbad
TEST=`flashrom --wp-enable; flashrom -{w,E}` on strongbad
Change-Id: I5dc66474a0b7969b51b86ac9f5daa2c95ae968f1
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Adding the title to About flashrom index page allows the engine
to recognise it as a group with a list of menu items inside, which
is as expected.
Without the title on the index page, all menu items inside About
flashrom are inlined into the menu.
Change-Id: I595acc282a536a6d5fa26cf2f8d18dbe549f9716
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77293
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Based on https://github.com/flashrom/flashrom/pull/204
squashed with fixes of IS25WQ040 size: it is 4Mbits, not 4MBytes, see
https://www.issi.com/WW/pdf/25WQ020-040.pdf
Tested read, write and erase with ft2232_spi-based "Tigard" programmer.
Change-Id: I072c6b94d7931637d1c2721c3316205f2d57320e
Signed-off-by: Roman Stingler <roman.stingler@gmail.com>
Signed-off-by: Vasily Galkin <galkin-vv@ya.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58179
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
e.g. when the shell is dash and sphinx-build is not installed, HAS_SPHINXBUILD would be wrongly set to yes.
Change-Id: I4d89e24ec3401446acec857eae134928bc3064d2
Signed-off-by: Bart De Schuymer <bdschuym@artinalgorithms.be>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77288
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Initial set of logo images had no ico file, so this patch
adds ico files, which are just conversion from png to ico.
Change-Id: I7238890833d84b3799e873c8a37b4176822ff9a4
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This is needed to include logo image on the docs root index page.
Change-Id: I38c1d820be92f2688c5fc4c63a150ab324d8b647
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77249
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested using the linux_spi programmer on a Raspberry Pi.
Datasheet:
https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L3255E.pdf
Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com>
Change-Id: I65968771e22e6b823d2d6192c33f5b0cba25d5b9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57410
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
People might be interested in what's currently ongoing in
development, and even more practically, have a look at examples
before creating their own patch. In fact, the latter is a good
idea to do. Giving the link in the intro of dev guide will
encourage that.
Viewing the patches does not require an account, so can be done
at the very beginning.
Change-Id: Iecd31a5e9a3683480b33fb9ba331545a0cf669b4
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/76771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
We can just say "follow the dev guide" here, the rest of information
should be in the dev guide.
Change-Id: Idf4df7426e5cf080416ba6691c7f11260c2b4623
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/76828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
While the process of migrating pages is ongoing, wiki can be useful
and is available in view-only mode.
Change-Id: I093dcb1d4ce2b3feeff61115e037cfa8075a8a52
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/76772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
