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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

3 Commits

Author SHA1 Message Date
Anastasia Klimchuk
84bfe0e04e tests: Add header stdlib.h to allow scan-build to do analysis
Without the header being explicitly included, scan-build run on CI
was returning errors for these files, such as:

include the header <stdlib.h> or explicitly provide a declaration
for 'calloc'

The functions in question were calloc, free, etc.

Change-Id: I4b79c5f86c074c456533296c309293e4064abe3f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84455
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25 01:46:27 +00:00
Alexander Goncharov
67e5c6afa4 tests: add probe lifecycle test for ch341a_spi
This test upgrades mocks to simulate a read request. Read buffer
is populated with chip manufacture id and chip model id to emulate
successful probing.

TEST=ninja test

Change-Id: I0a2d5591d097435fc69719e1d9bd153433425821
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2022-11-29 21:07:43 +00:00
Alexander Goncharov
d0fc4e76e1 tests: add basic lifecycle test for ch341a_spi
TEST=the following scenarios run tests successfully

1) ch341a_spi is enabled
result: all tests run and pass, including ch341a

2) ch341a_spi is disabled
result: ch341a_spi test is skipped, the rest of tests run and pass

3) libusb isn't presented in the system
result: tests for usb programmers are skipped, the rest of tests run
normally

Change-Id: If28fbe09ad685082152aa3a7e8d5a150169aee9e
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2022-11-29 21:05:00 +00:00