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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 07:02:34 +02:00

4 Commits

Author SHA1 Message Date
Anastasia Klimchuk
84bfe0e04e tests: Add header stdlib.h to allow scan-build to do analysis
Without the header being explicitly included, scan-build run on CI
was returning errors for these files, such as:

include the header <stdlib.h> or explicitly provide a declaration
for 'calloc'

The functions in question were calloc, free, etc.

Change-Id: I4b79c5f86c074c456533296c309293e4064abe3f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84455
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25 01:46:27 +00:00
Jes B. Klinke
ea91d4fcf4 raiden: Support target index with generic REQ_ENABLE
Some devices such as the GSC knows how it is wired to AP and EC flash
chips, and can be told which specific device to talk to.  Other devices
such as Servo Micro and HyperDebug are generic, and do not know how they
are wired, the caller is responsible for first configure the appropriate
MUXes or buffers, and then tell the debugger which port to use (Servo
Micro has just one SPI port, HyperDebug is the first that has multiple).
The Raiden protocol allows both the cases of USB devices knowing their
wiring and not.

If I were to declare the protocol in Rust, this is how the information
of the Raiden protocol "enable request" would be encoded:
```
enum {
  EnableGeneric(u8),
  EnableAp,
  EnableEc,
  ...
}
```

The first label `EnableGeneric(u8)` is to be used with HyperDebug that
does not know how its ports are wired, and allow access by index.
The other labels `EnableAp` and `EnableEc` are to be used with the GSC.

The actual transmission of the enum above uses the bRequest and low byte
of wValue of a USB control request, but that is a detail and not
conceptually important.

Until now, `-p raiden_debug_spi:target=AP` or `...:target=EC` could be
used to make flashrom use `EnableAp` or `EnableEc`, and if neither was
given, it would default to `EnableGeneric`, which now that wValue is
used means `EnableGeneric(0)`.

I find it rather straight-forward, that `-p raiden_debug_spi:target=1`,
`...:target=2`, etc. should translate to `EnableGeneric(1)`, etc.

This patchset achieves this, by adding a second 16-bit parameter value,
next to request_enable.

I have tested that flashrom can detect the same Winbond flash chip
"W25Q128.V..M" with two different Raiden USB devices as below.

TEST=flashrom -p raiden_debug_spi:serial=0701B044-91AC3132,target=AP
TEST=flashrom -p raiden_debug_spi:serial=205635783236,target=1

Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I03bf4f3210186fb5937b42e298761907b03e08b7
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2023-11-03 05:59:53 +00:00
Edward O'Callaghan
dd41980f17 tests/: Assert on NULL heap allocations in tests
Change-Id: Id2adcfe859fb25d2a7f0734655c6b9a58c0890b6
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/71919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2023-01-22 05:56:12 +00:00
Anastasia Klimchuk
94efa44542 tests: Split lifecycle test file into per-programmer files
This patch creates individual files for each programmer's lifecycle
tests. Common functions that are reusable for all tests are
gathered in lifecycle.c. Each individual file needs to include
lifecycle.h

BUG=b:237606255
TEST=ninja test

Change-Id: If2307699dcbb3a085b91a2dcd41156e6fd07f812
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65543
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-10 22:28:45 +00:00