If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.
Corresponding to flashrom svn r352 and coreboot v2 svn r3780.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This has been tested by Uwe Hermann on an RS690/SB600 board.
Corresponding to flashrom svn r351 and coreboot v2 svn r3779.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID
RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.
The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES
Corresponding to flashrom svn r349 and coreboot v2 svn r3775.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Although SPI itself does not have a mechanism to signal command failure,
the SPI host may be unable to send a given command over the wire due
to security or hardware limitations. The current code ignores these
mechanisms completely and simply assumes almost every command succeeds.
Complain if SPI command execution fails.
Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.
Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.
Corresponding to flashrom svn r345 and coreboot v2 svn r3757.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.
Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D
Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642
Add the ID, but no probing function for this chip:
AT25F512A
Corresponding to flashrom svn r342 and coreboot v2 svn r3754.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>
Not all chips support all commands, so allow the implementer to select
the matching function. Fix a layering violation in ICH SPI code to be
less bad. Still not perfect, but the new code is shorter, more generic
and architecturally more sound.
TODO (in a separate patch): - move the generic sector erase code to
spi.c - decide which erase command to use based on info about the chip -
create a generic spi_erase_all_sectors function which calls the generic
sector erase function
Thanks to Stefan for reviewing and commenting.
Corresponding to flashrom svn r337 and coreboot v2 svn r3722.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Using block erase d8 as discussed with Peter Stuge
Corresponding to flashrom svn r333 and coreboot v2 svn r3707.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r326 and coreboot v2 svn r3669.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines, whereas writing
resort to the recent write_en29f002a(), since also these chips use a
byte wise algorithm.
Corresponding to flashrom svn r321 and coreboot v2 svn r3639.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Fully tested for Probe/Read/Erase/Write on EN29F002NT.
Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
are still in use, but a tailored 'write_en29f002a()' is
needed due to a byte wise writing mechanism for this chip.
Corresponding to flashrom svn r316 and coreboot v2 svn r3602.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.
The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.
Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.
Corresponding to flashrom svn r304 and coreboot v2 svn r3431.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.
I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.
Corresponding to flashrom svn r302 and coreboot v2 svn r3418.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Flash.h is a database of known IDs, whereas flashchips.c is a database
of chips for which support has been implemented. Keep it that way.
Corresponding to flashrom svn r300 and coreboot v2 svn r3416.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch adds support to the AMIC A29002 chip in its top and bottom
configuration to flashrom. Additionally, the alphabetic order of the
AMIC chips was fixed.
The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.
A29002T PREW functionality was tested and works.
This flash chip has asymmetric sector layout so it is important to use the
mx29f002 driver, which does chip erase before writing, rather than am29f040b,
which uses sector erase.
Corresponding to flashrom svn r299 and coreboot v2 svn r3415.
Signed-off-by: Andreas Thienemann <andreas@bawue.net>
Acked-by: Peter Stuge <peter@stuge.se>
At some point the flash bus will be part of struct flashchip.
Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.
Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.
Corresponding to flashrom svn r285 and coreboot v2 svn r3401.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Following patch adds support for that.
Corresponding to flashrom svn r283 and coreboot v2 svn r3399.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
It is similar with few documented exceptions to ICH7 SPI controller.
Corresponding to flashrom svn r282 and coreboot v2 svn r3398.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
* ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)
Corresponding to flashrom svn r278 and coreboot v2 svn r3393.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
DOC support has been disabled by default for many years. The write function
does nothing but print text. It has a call to write_page_md2802() commented
out, but that function does not exist. This is dead code with ugly #ifdefs.
Updates README to reflect that there was a time when there was code, but it
didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.*
Corresponding to flashrom svn r269 and coreboot v2 svn r3382.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Jens sent the first patch that added A49LF040A to flash.h and flashchips.c
using _jedec and _49lf040 functions.
An issue was found with probe_w29ee011() for the Winbond W29EE011, which
caused the A49LF040A to no longer respond to any commands.
Ward made a patch to disable probing by default for the W29EE011 following
some discussion. Using -c W29EE011 will make flashrom probe for the chip.
Peter did some more datasheet diving and found that the Pm49FL00x functions
suited this chip quite well because of the block locking registers in
A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3.
Ward confirmed that this works on alix.2c3 too.
Corresponding to flashrom svn r260 and coreboot v2 svn r3368.
Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
When flash chip detection fails, it is still useful and possible to read the
flash chip contents. If no flash chip is found in normal probes and the
-f -r -c CHIPNAME options are given, a successful probe for the specified
chip is forced, and then flashrom reads the flash chip using either the read
function for the specified chip, or if there is none, a simple memcpy().
The patch also moves the global variable int force in flashrom.c into main()
and passes it as a parameter to layout.c:show_id(), which was the only other
function that used the variable. This is needed to avoid confusion with the
new parameter int force which is added to flashrom.c:probe_flash() and used
to force probe success for the chip named in char *chip_to_probe.
Corresponding to flashrom svn r259 and coreboot v2 svn r3367.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
Corresponding to flashrom svn r254 and coreboot v2 svn r3358.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Corresponding to flashrom svn r246 and coreboot v2 svn r3345.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch addresses different argument order of outX() calls,
FreeBSD-specific headers, difference in certain type names and system
interface names, and also FreeBSD-specific way of gaining IO port
access.
Corresponding to flashrom svn r245 and coreboot v2 svn r3344.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.
This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c
Thanks go to Nikolay for this patch.
Corresponding to flashrom svn r243 and coreboot v2 svn r3332.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>
This is done by using the generic SPI interface.
Corresponding to flashrom svn r239 and coreboot v2 svn r3325.
Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Only a subset has been added to flashchips.c, but the IDs in flash.h
will make lookups easier if anybody wants to add support for them.
Corresponding to flashrom svn r236 and coreboot v2 svn r3321.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Add support for the JEDEC RES (Read Electronic Signature and Resume from
Powerdown) SPI command to identify older SPI chips which can't handle
JEDEC RDID.
Since RES gives a one-byte identifier which is shared among many
different vendors and even different sizes, we want to match RES as a
last resort if RDID returns 0xff 0xff 0xff.
Corresponding to flashrom svn r235 and coreboot v2 svn r3320.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>
Flash chips which can be detected by JEDEC probe routines all have
vendor IDs with correct parity. Use a parity check as additional hint
whether a vendor ID makes sense. Note: Device IDs have no parity
requirements whatsoever.
Corresponding to flashrom svn r231 and coreboot v2 svn r3308.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Add a few flashchips already mentioned in flash.h to flashchips.c
Corresponding to flashrom svn r230 and coreboot v2 svn r3306.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
SST39VF040 has been confirmed to probe OK by misi e.
Corresponding to flashrom svn r226 and coreboot v2 svn r3300.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The SST39LF series has the same IDs. Add short AMIC vendor ID to
flashrom.
Corresponding to flashrom svn r225 and coreboot v2 svn r3299.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This is a very early step toward cleaning up SPI code in flashrom.
Corresponding to flashrom svn r223 and coreboot v2 svn r3295.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.
All chips are TEST_UNTESTED for now.
Corresponding to flashrom svn r221 and coreboot v2 svn r3277.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The generic jedec.c does not work for the ST M50FLW flash devices,
because they need an unlock command first. For this reason, ST M50FLW
support is moved to a new HW support module, because any change in
jedec.c would bear the risk to cause problems with the already supported
devices.
It's already tested with ST M50FLW080A; the other chips of this family i
dont have available, so i couldnt test it.
Corresponding to flashrom svn r219 and coreboot v2 svn r3274.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Support for flashing on the Kontron 986LCD-M board.
Corresponding to flashrom svn r213 and coreboot v2 svn r3165.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Corresponding to flashrom svn r209 and coreboot v2 svn r3146.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.
Corresponding to flashrom svn r203 and coreboot v2 svn r3139.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Some vendors like Programmable Micro Corp (PMC) need this. Both the
serial and parallel flash JEDEC detection routines would benefit from a
parity/sanity check of the vendor ID. Will do this later.
Add support for the PMC Pm25LV family of SPI flash chips.
Corresponding to flashrom svn r191 and coreboot v2 svn r3091.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
Corresponding to flashrom svn r178 and coreboot v2 svn r3054.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r173 and coreboot v2 svn r3032.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
