For all tests that exist as of today, drivers are built by default,
however config options can be disabled and in that case test should
not be run.
Technically, this is done by skipping the test.
BUG=b:181803212
TEST=1) Tested by adding into tests/meson.build
-DCONFIG_xxx=0
4 times (for every driver with test), and then running ninja test
Result: corresponding test is skipped, all other tests are passed
2) Running ninja test with default config settings (everything is
enabled, no overriding in test meson).
Result: all tests are passed.
3) Replacing one of config options in the patch with CONFIG_JLINK_SPI
which is disabled by default.
Result: corresponding test is skipped.
Change-Id: Ic1c48e41f658045a608f46636071f478ba646f77
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reword the message and drop the error string from libftdi. It is
already printed in send_buf().
Change-Id: I125ae9ec0d5487fc26d588a7fd6c54da4ebd0d70
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
We missed to `free(spi_data)` on one path. It also seems odd to leak
the return code of a locally used library into our common infrastruc-
ture, so normalize all error paths to return 1.
Change-Id: I5158d06127a9a8934b083e48b69d29c4d5a11831
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The meaning of the variables is easy to misunderstand as some
states are merely implicit: All output pins that are not set
in the `cs_bits` mask will be constantly driven low. This may
be sheer coincidence as all programmers that need additional
pins driven use active-low signals to enable buffers.
While other pins stay low, *all* pins set in the `cs_bits`
mask are supposed to be toggled during SPI transactions.
Also drop some irritating dead code and try to explain things
in a comment.
Change-Id: I2b84ede01759c80f69d5ad17e43783d09ecd1107
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit ba6575de82f091b97ea0f2efcf2f79ef3739d64f.
Technically, the only thing that is wrong here is the lack of docu-
mentation (manpage update). However, as this change was succeeded by
a regressing fixup patch, it seems likely that the meaning of the
`csgpiol` parameter was just misunderstood and these changes were
not what the author intended.
Change-Id: I460237b9d275b1cd1d8a069f852d17dea393b14e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.
Nothing was broken. So this breaks everything. Well, actually only
the `csgpiol` parameter. But that is very obvious.
`csgpiol` was added to use a GPIO pin as /CS. But this change impli-
citly hardcoded /CS to ADBUS3.
Change-Id: I9ecdfe227585dda74658c16c96a57dd42d1d78b4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This reverts commit 3207844ec0b5dc16f9ae9ee45294213dbf6d060b.
It used the `cs_bits` variable for its own purpose (not CS) which
was only possible because the `cs_bits` semantics were broken earlier.
It also lacks an update to the manpage.
Change-Id: I4a95317b1cf1fc6df9471d0cfb8a6a8f40964fe3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 180079632b15758ca0bbbe5782611bd4573e11d8.
The renaming only seemed to match the code because of earlier introduced
regressions (see following reverts). For proper support of the `gpiol`
feature, we'd likely need both a `cs_bits` and a `pinlvl` variable.
Change-Id: Ifa5b2259ccf49ddf729d01176bacd94a95c39925
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Now that ft2232_spi_send_multicommand() is implemented, we don't need
the single-command version anymore.
Change-Id: I2e7fa1046e260f490b881a33e02ad73d16f0a30c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This "chunk size" limits the amount of data that is passed to libusb
at once. If we had exceeded the chunk size, libftdi would have split
the data into individual, synchronous bulk transfers. But the chunk
size was actually chosen to avoid this. So without any known effect,
setting the chunk size is useless. Drop it.
Change-Id: I779e24dc3f3379a98ddce02c3765062ac3241884
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Every ftdi_write_data() call is quite time consuming as the ftdi-chips
seems to take always 2-3ms to respond. This leads to what the comment
already says: Minimize USB transfers by packing as many commands as
possible together. So I packed the WREN command together with the
following operation which can be program or erase operation.
This saves about 1 minute when programming a 128MBit Flash within a
virtualized setup.
Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Both of these headers are only used in test builds, so they should
live in tests/ directory. No changes to meson.build and
tests/meson.build files are needed because tests/meson.build adds
current directory to search for include files.
BUG=b:181803212
TEST=ninja test
-> all tests pass
nm builddir/tests/flashrom_unit_tests.p/.._it85spi.c.o
-> has symbols _test_calloc, _test_free, test_inb, test_outb
nm builddir/flashrom.p/it85spi.c.o
-> has symbols calloc free inb outb
Change-Id: Ia42773b98b1eb6c65241aa559c0c8b4926bd0814
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This change adds a 'psus=<on|off>' option, to control the external Vcc
state of the bus pirate, allowing hardware where the SPI flash chip is
powered by the 3V3/5V lines directly.
Change-Id: I8a7d4b40c0f7f04f6976f6757f05b61f2c9958f9
Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The name of the struct type already contains bp_ prefix, so
prefix doesn't need to be repeated in members name.
BUG=b:185191942
TEST=builds
Change-Id: Ia463e3f58497e4b10be072bdd29244f4868098e7
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move global singleton states into a struct and store within
the spi_master data field for the life-time of the driver.
This is one of the steps on the way to move spi_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
BUG=b:185191942
TEST=builds
Change-Id: I418bbfff15fb126b042fbc9be09dbf59f4d243b8
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52958
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Shutdown function was covering two different jobs here: 1) the actual
shutdown which is run at the end of the driver's lifecycle and
2) cleanup in cases when initialisation failed. Now, shutdown is only
doing its main job (#1), and the driver itself is doing cleanup
when init fails (#2).
The good thing is that now resources are released/closed immediately
in cases when init fails (vs shutdown function which was run at some
point later), and the driver leaves clean space after itself if init
fails.
And very importantly this unlocks API change which plans to move
register_shutdown inside register master API, see
https://review.coreboot.org/c/flashrom/+/51761
BUG=b:185191942
TEST=builds
Change-Id: I04d57e2552d23a1a4a906c68539f0ccefc13e8a0
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52877
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
const char **flashrom_supported_programmers(void) returns an array of
strings without returning the array size or making a NULL
termination. This can lead to undefined behavior when iterating over the
array.
Change-Id: I0157926a654e337c14d840dd398e5576471c304f
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55350
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Process the "upper map" early as it doesn't depend on the descriptor
generation. This way, we can use it to guess the generation.
Change-Id: Ia2786b762ccefdce31b63397119bd89879e887ff
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Correct "firmware descriptor" to "flash descriptor". And also
move the check for peculiar descriptors and the message into an
inline function.
Change-Id: I7f15780e03d2fa17ca6d8328275cae5af13ae424
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55644
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Programmer initialization stops the on-chip MPU, and it was never
restarted. Leaving it stopped seems to prevent some display detection
from working, so implement restarting the MPU on programmer shutdown.
BUG=b:190359231
TEST=display hotplug works reliably after device communication
Change-Id: I66cd68f8f6905a2bfaf5b085bf08dcb218f42855
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
The definition of external structs doesn't have to be guarded.
See discussion under review.coreboot.org/52946.
Change-Id: I01e6a785269c3e0bd648eeaee217a7a855ab0853
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Using the pointer's type instead ensures that we get the right size even
if code changes in the future.
Change-Id: If88ba394095f86c598dcc5cf1751e1c23b132d04
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
As mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020.
Change-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618
Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move global singleton states into a struct and store within
the par_master data field for the life-time of the driver.
This is one of the steps on the way to move par_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
BUG=b:185191942
TEST=builds
Change-Id: If0cb0fefb53b2c6bb65a85f4c8dc6f323954dd0c
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
CONFIG_DEFAULT_PROGRAMER_NAME replaces CONFIG_DEFAULT_PROGRAMMER.
It uses the name of the programmer for identification.
make CONFIG_DEFAULT_PROGRAMER_NAME=dummy and
meson -Ddefault_programmer_name=dummy will extend to
CONFIG_DEFAULT_PROGRAMER_NAME=&programmer_dummy in the code.
Change-Id: I976447787c6f6bfbdc0145d80d61e1ddcf97ac33
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to the W25Q64JW datasheet rev. E, only devices ending with the
letter 'M' have a device ID of 8017h. There are other variants with
different device IDs. This patch makes the 'W25Q64JW...M' definition
consistent with the 'W25Q32JW...M' definition.
The device ID macro defined in flashchips.h has also been renamed from
WINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.
BUG=b:166294558
BRANCH=none
TEST=builds
Change-Id: Ib0dc914da286a191d22e666332b1063b88db4251
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The chip was added to cros flashrom in
`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.
Quoting from the commit message:
> We have varied the correct chip name is reported as well as
> write and read 16MBytes of random data and verified the checksum's match.
> Further, --wp-list appears to report the correct ranges.
>
> BUG=b:130199963
> BRANCH=none
> TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched.
Change-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Simply provide an initialiser or use a direct assignment instead.
Change-Id: I07385375cd8eec8a95874001b402b2c17ec09e09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Spelling out the struct type name hurts readability and introduces
opportunities for bugs to happen when the pointer variable type is
changed but the corresponding sizeof is (are) not.
TEST=`make CONFIG_EVERYTHING=yes CONFIG_JLINK_SPI=no VERSION=none -j`
with and without this patch; the flashrom executable does not change.
Change-Id: Icc0b60ca6ef9f5ece6ed2a0e03600bb6ccd7dcc6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The `EMULATE_CHIP` and `EMULATE_SPI_CHIP` macros are unconditionally
defined as `1`, with no way to change their values. Since this means
that the code never gets build-tested using other values, drop these
noisy macros.
TEST=Build with `make distclean && make VERSION=none -j` with and
without this patch, the flashrom executable does not change.
Change-Id: If46e1c37c3b04b28b4ba1f82c9b3def1e549368f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@google.com>
Move global singleton states into a struct and store within
the par_master data field for the life-time of the driver.
This is one of the steps on the way to move par_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
BUG=b:185191942
TEST=builds
Change-Id: I9834b82650cd070556cf82207796bc6bd6b31b28
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allows us to move the individual entries into their respective driver files.
Change-Id: Ifbb0ee4db5a85b1cd2afeafe4dca838579f79878
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Makes the array size known to other compilation units.
Change-Id: Idacb4b7b0dd98af8bc7cbecf567d33daafb4b24d
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55116
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The {0} object at the end of programmer_table which corresponds
to PROGRAMMER_INVALID has no use in current code.
Change-Id: Ib63c2d2941f23a0788e26e5a5feb25d8669acb42
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch extracts params processing into a separate function. Now
all error paths of params processing return 1 back to init function
which frees data.
And there was just one more error path in init function where
free(data) needed to be added.
This is a follow up on commit 3b8fe0f8e907c0ba9f7c7935e950f3e1538d427f
which moves global state into spi_master data.
A good side-effect of the change is: init function becomes easier
to read.
BUG=b:185191942
TEST=ninja test
Change-Id: I04f55f77bb4703f1d88b2191c45a22be3c97bf87
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Building flashrom on Apple Silicon Macs fails with
"Unable to determine endianness" error. It seems that current
endianness detection fails on macOS due to a combination of
three issues:
1. On macOS, neither GCC nor Clang have __ARMEL__ macros used
by architecture-specific detection;
2. Generic detection fails because Apple uses LITTLE_ENDIAN,
BIG_ENDIAN and BYTE_ORDER macros instead of __BYTE_ORDER and
__LITTLE_ENDIAN;
3. In platform.h, __LITTLE_ENDIAN__ and __BIG_ENDIAN__ macros
are checked only for PowerPC architecture.
This error can be fixed by appending __LITTLE_ENDIAN__ and
__BIG_ENDIAN__ to conditions in IS_ARM branch. I've considered
multiple approaches, but this one seems the cleanest to me.
Signed-off-by: Ivan V <root@pcm720.me>
Change-Id: Ifdb1523ee2c7023e657cfd7b823b091d5deef513
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
