Turns out that the AMD 8111 datasheet describes this bit of the MCP
perfectly.
Corresponding to flashrom svn r792.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
All AK31 versions, 1.x, 2.x and 3.x are supported by this board enable.
Sadly this board can not be autodetected.
Re-uses the epox ep 8k5a2 board enable, which now lost its check for
the VT8235 ISA bridge and got renamed to w836xx_memw_enable_2e.
Corresponding to flashrom svn r790.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mateusz Murawski <matowy@tlen.pl>
* Add autodetection and remove match strings.
* Make use of vt823x_set_all_writes_to_lpc.
Corresponding to flashrom svn r789.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Sean Nelson <audiohacked@gmail.com>
This code sets gpio lines on random intel ichs. Detects all currently
known intel ICHs, checks gpio lines, and then sets them accordingly.
Corresponding to flashrom svn r786.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Idwer Vollering <vidwer@gmail.com>
The deleted function in en29f002a.c is reintroduced as
write_by_byte_jedec in jedec.c as it contains no chip-specific
instructions. It is not yet used in other chip drivers, as key addresses
(0x2AAA/0x5555) are often specified with less bits. After crosschecking
datasheets, most of the fixmes can probably be resolved as indicated in
them, causing significant code reduction.
The common JEDEC code for bytewise programming does not program 0xFF
at all. The chips that had a dedicated bytewise flash function which
has been changed to write_jedec_1 thus changed flashing behaviour
and the "write" test flag has been removed. This applies to: AMD
Am29F002BB/Am29F002NBB AMD Am29F002BT/Am29F002NBT (TEST_OK_PREW before)
AMIC A29002B AMIC A29002T (TEST_OK_PREW before) EON EN29F002(A)(N)B EON
EN29F002(A)(N)T (TEST_OK_PREW before) Macronix MX29F001B (TEST_OK_PREW
before) Macronix MX29F001T (TEST_OK_PREW before) Macronix MX29F002B
Macronix MX29F002T (TEST_OK_PREW before) Macronix MX29LV040
Similar analysis should be performed for the read id stuff.
Corresponding to flashrom svn r785.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Found in Intel document 322170 (Intel 5 Series Chipset and Intel 3400
Series Chipset Specification Update).
According to http://pciids.sourceforge.net/ we probably should match all
IDs from 0x3b00-0x3b1f, but so far I didn't find an Intel doc saying the
same.
If anybody has contacts at Intel and can check, I'd be happy to add the
rest of the IDs.
Corresponding to flashrom svn r784.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
This patch removes the extremely dangerous unprotect_jedec function
which is not used at all within flashrom code, and renames the
misleadingly named protect_jedec function to start_program_jedec.
Calls to protect_jedec after flashing are removed, because a) on LPC
chips, the command sent by protoct_jedec is not even in the datasheet
and b) on parallel chips, the block write command issued before already
contained the software protection sequence, so software protection is
definitely enabled.
This patch also removes two clones of protect_jedec
Background: JEDEC Software Data Protection started as an optional
feature, which was disabled on the first single-voltage-flash chips.
The software data protection is the need to prefix a write with a magic
"write enable" command, while without write protection every write
access into the chip's address space modifies flash content. This magic
write enable command also tells the flash chip that the programmer
obviously support sending write-enable commands and turns off the "any
write modifies flash content" mode. There also exist a two-command (6
writes) sequence that disables Software Data Protection completey, which
should only ever be used to prepare updating with a device that can't
handle software data protection.
Corresponding to flashrom svn r783.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The model_ids are already in the header.
W25x32 has been successfully probed. W25x64 is not available, the entry
is based on the datasheet.
Corresponding to flashrom svn r782.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
FT2232 ran realloc() for every executed command. Start with a big enough
buffer and don't touch buffer size unless it needs to grow.
Bitbang was slightly better: It only ran realloc() if buffer size
changed. Still, the solution above improves performance and reliability.
Corresponding to flashrom svn r780.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
Fix. jedec.c error handling used double negation in too many places for
no good reason. Clean up.
Corresponding to flashrom svn r779.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
Now uses block erase instead of chip erase. Also introduced auto skip
feature.
Corresponding to flashrom svn r778.
Signed-off-by: Adam Jurkowski <adam.jurkowski@kontron.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The existing code does not work for all SPI chips, and it just was a
band-aid to cope with locked down chipsets back in a time when there was
no eraseblock infrastructure.
Basically, this unbreaks a few SPI chips on ICH.
Corresponding to flashrom svn r777.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Example usage:
flashrom -p buspiratespi:spispeed=2.6MHz,dev=/dev/foo
flashrom -p buspiratespi:dev=/dev/foo,spispeed=2.6M
Refactor programmer option parsing (this allows cleanups in other
programmers as well).
Increase SPI read size from 8 to 12 bytes (current single-transaction
limit of the Bus Pirate raw SPI protocol).
Add Bus Pirate to the list of programmers supporting 4 byte RDID.
Add Bus Pirate syntax to the man page.
Tested-by: Sean Nelson <audiohacked@gmail.com>
Corresponding to flashrom svn r776.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
This chip is sometimes labeled as 25FW203T.
Corresponding to flashrom svn r775.
Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Corresponding to flashrom svn r774.
Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The code should work on Linux/*BSD/MacOSX and relies on the serial code
implementation in serial.c. Support for additional platforms (Windows)
will have to be added to serial.c for this to work. For tests without a
Bus Pirate (or with non-functional serial code) it is possible to
#define FAKE_COMMUNICATION in buspirate_spi.c.
Thanks to Sean Nelson for the SPI mode settings code. I tweaked it a bit
to make configuration from a commandline easier should anybody want that
feature.
Tested-by: Sean Nelson <audiohacked@gmail.com>
Corresponding to flashrom svn r772.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Sean Nelson <audiohacked@gmail.com>
This is the first step in enabling platform independent serprog and it
also allows other drivers to use serial port functionality without
requiring serprog.
Pure code move, no code changed.
Corresponding to flashrom svn r771.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This will be useful once we create a --test function for flashrom.
The test patterns make it easy to find skipped and duplicated bytes, are
human readable, and the first 8 of them have block numbers to detect
aliasing or wraparounds. Current size limit for aliasing detection is
16 MByte, but since neither LPC nor FWH nor SPI chips exist with bigger
sizes, this is reasonably safe.
Detailed documentation is available as source code comments above the
new function generate_testpattern().
Corresponding to flashrom svn r770.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Pretty much everybody who used the FT2232 SPI driver had problems with
incorrect reads from time to time. One reason was that the hardware is
pretty timing sensitive even for reads.
The other reason was that the code silently ignored errors. This patch
doesn't add any error recovery, but it will emit error messages if
FT2232 communication goes wrong. That allows us to track down errors
without investing hours in driver debugging.
Thanks to Jeremy Buseman <naviathan@gmail.com> for testing. He found out
that certain libftdi/libusb/kernel/hardware combinations drop some bytes
without returning any error codes.
Corresponding to flashrom svn r769.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Paul Fox <pgf@laptop.org>
Serprog already has such functionality, so it makes sense to share that.
TODO: Factor out serial communication into a separate file, have that
code be available even if serprog is not selected and make it portable
(it is very Linux-centric right now).
Corresponding to flashrom svn r768.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
If a chip is not on the RDID generic vendor list nor on the REMS
specific ID list, flashrom will claim that no chip is there.
Handle these cases gracefully. flashrom will ignore generic matches if a
specific chip was found, so this will have no impact on supported chips,
but help a lot for a first quick analysis by the user or developer. The
only drawback is that unknown chips may be recognized multiple times
until they are added to flashchips.[ch].
Corresponding to flashrom svn r767.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>
To prepare for libflashrom I wanted to make the main loop more readable and more correct and factor out stuff which can be useful in libflashrom.
- Factor out printing of supported devices to print.c.
- Adjust name of wiki printing function to fit the pattern.
- Abort if the user specified --verify and --noverify at the same time.
- Check for extra parameters which don't fit commandline syntax.
Corresponding to flashrom svn r766.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Vincent wrote: This patch provided help to debug the partial write on
ICH in descriptor mode.
Corresponding to flashrom svn r764.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Vincent S. Cojot <openlook@cojot.name>
Add a note for ASUS M2N-E.
Change "iff" to "if". Most people don't understand what "iff" means and
the meaning of both words is close enough to hopefully give users the
right idea.
Corresponding to flashrom svn r763.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Retrieve the proper linker flags for libftdi via pkg-config and fall
back if pkg-config isn't available or if it doesn't know libftdi.
Fix $LIBS and $FEATURE_LIBS to honor dependency order.
The original patch is from Jörg, it has been updated by Carl-Daniel to
work on the current tree and to have a fallback in case pkg-config is
not available or not working.
Corresponding to flashrom svn r762.
Signed-off-by: Jörg Mayer <jmayer@loplof.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jörg Mayer <jmayer@loplof.de>
Mark SiS 735 as supported.
Remove "SiS" from the model number to avoid printing it twice.
Reported by Adrian Glaubitz.
Corresponding to flashrom svn r760.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The two existing SiS chipset enables (compared to the 28 in this patch)
were refactored, and one of them was fixed.
A function to match PCI vendor/class combinations was added to generic
code.
Tested on the "Elitegroup K7S5A". Results are somewhat unexpected (some
PCI settings seem to be inaccessible, but it still works).
This is not based on any docs, but rather on detailed analysis
of existing opensource code for some of the chipsets.
Thanks to for Adrian Glaubitz testing.
Corresponding to flashrom svn r759.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Reported by martin f krafft <madduck@madduck.net>
Mark "Asus K8V SE Deluxe" as supported. Reported by Luke Dashjr
<luke_coreboot@dashjr.org>
Corresponding to flashrom svn r758.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The automatic retry in write_page_write_jedec didn't retry flashing the
correct range, essentially rendering the functionality useless.
This patch simplifies the code and fixes the bug.
Thanks to Luke Dashjr for testing.
Mark Winbond W29C040P as supported.
Corresponding to flashrom svn r757.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luke Dashjr <luke_coreboot@dashjr.org>
The rationale is to warn users when they, for example, try to flash
a 512KB parallel flash chip but their chipset only supports 256KB,
or they try to flash 512KB and the chipset _does_ theoretically
support 512KB but their special board doesn't wire all address lines
and thus supports only 256 KB ROM chips at maximum.
This has cost Uwe hours of debugging on some board already, until he
figured out what was going on. We should try warn our users where
possible about this.
The chipset and the chip may have more than one bus in common (e.g.
SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there
are different limits for LPC and FWH. The only way to tell the user
about the exact circumstances is to spew error messages per bus.
The code will issue a warning during probe (which does fail for some
chips if the size is too big) and abort before the first real
read/write/erase action. If no action is specified, the warning is
printed anyway.
That way, a user can find out why probe might not have worked, and will
be stopped before he/she gets incorrect results.
Add a bitcount function to the infrastructure.
Corresponding to flashrom svn r755.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Pointed out by Maciej Pijanka.
Corresponding to flashrom svn r754.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Since we don't have any debug level printing infrastructure yet, I
propose to kill the obnoxious debug message in ichspi.c which was added
to check for correct PREOP handling.
We know the code works fine (after getting a few reports over 100 MB
long) and there's no point in keeping it around anymore. If there is any
desire, we can reinstate it as print_spew or whatever once the debug
level infrastructure is merged, but at that point we probably just are
happy that the debug output isn't there anymore.
Corresponding to flashrom svn r753.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
Shuttle SFF PC is SN25P, board FN25, AMD socket 939 with an nForce4
chipset.
Config register 0x92 on the ISA bridge needs to be cleared for TBL#
to be raised. No information about individual bits of this register
is currently available.
Corresponding to flashrom svn r752.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Ulf Mehlig <ulf@ufpa.br>
- MSI MS-6153 (reported by Uwe Hermann <uwe@hermann-uwe.de>)
Tested by me on hardware. The board decodes max. 256 KB.
- MSI MS-6156 (reported by Uwe Hermann <uwe@hermann-uwe.de>)
Tested by me on hardware. The board decodes max. 256 KB.
Also, fix Dell PowerEdge 1850 name and add some more board URLs.
Corresponding to flashrom svn r749.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
SocketA + nForce2 + MCP2.
Motherboard includes a second ethernet controller and an Agere
firewire controller with valid subsystem ids, so these are used for
matching the board.
Corresponding to flashrom svn r746.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Eddie Vanhove <moonraket@hotmail.com>
This patch reorganises the board_ga_k8n_sli to create
nvidia_mcp_gpio_raise, a more general routine to set these bits.
Without docs, i can only assume that these memory area are gpio
lines.
Then it becomes easy to add support for this nForce4 SLI board.
Corresponding to flashrom svn r745.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Martin Szulecki <opensuse@sukimashita.com>
Add pciids for the new isa bridge, and hook it to the nforce2
chipset enable.
Corresponding to flashrom svn r744.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Martin Szulecki <opensuse@sukimashita.com>
So far, the only case where libz is needed is when a library (libpci)
pulls in libz and even then it only happens if libpci is available in a
static version only and said static version has libz requirements.
Check for libpci separately and don't require libz if it isn't needed.
Clarify the README.
Corresponding to flashrom svn r743.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
