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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

110 Commits

Author SHA1 Message Date
Stefan Reinauer
4311956a80 Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead
This is slightly slower (ha, ha), but works on boards with a locked
opmenu. Tested on ICH7 and works.

Corresponding to flashrom svn r336 and coreboot v2 svn r3721.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-11-02 19:51:50 +00:00
Uwe Hermann
394131ef14 Coding-style fixes for flashrom, partly indent-aided
Corresponding to flashrom svn r326 and coreboot v2 svn r3669.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-10-18 21:14:13 +00:00
Peter Stuge
6a214163c0 Trivial indent fix in ichspi.c
Corresponding to flashrom svn r301 and coreboot v2 svn r3417.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
2008-07-07 05:14:06 +00:00
Stefan Reinauer
2cb94e183b First attempt to clean up SPI probing and create a common construct: the flash bus
At some point the flash bus will be part of struct flashchip.

Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.

Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.

Corresponding to flashrom svn r285 and coreboot v2 svn r3401.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-06-30 23:45:22 +00:00
Rudolf Marek
3fdbccf697 This patch adds support for VIA SPI controller on VT8237S
It is similar with few documented exceptions to ICH7 SPI controller.

Corresponding to flashrom svn r282 and coreboot v2 svn r3398.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
2008-06-30 21:38:30 +00:00
Carl-Daniel Hailfinger
10693353ee Add a debug marker after ICH SPI opcode programming
Corresponding to flashrom svn r281 and coreboot v2 svn r3397.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-06-29 10:57:13 +00:00
Peter Stuge
7e2c079367 Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.

Also fixes a build error in ichspi.c with gcc 4.2.2.

Corresponding to flashrom svn r280 and coreboot v2 svn r3395.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-06-29 01:30:41 +00:00
Stefan Reinauer
a9424d597d Multiple unrelated changes
* ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)

Corresponding to flashrom svn r278 and coreboot v2 svn r3393.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
2008-06-27 16:28:34 +00:00
Stefan Reinauer
325b5d47d8 Indent according to development guidelines
Corresponding to flashrom svn r277 and coreboot v2 svn r3392.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-06-27 15:18:20 +00:00
Dominik Geyer
b46acba6e0 Add support for SPI chips on ICH9
This is done by using the generic SPI interface.

Corresponding to flashrom svn r239 and coreboot v2 svn r3325.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-05-16 12:55:55 +00:00