1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

105 Commits

Author SHA1 Message Date
Carl-Daniel Hailfinger
10693353ee Add a debug marker after ICH SPI opcode programming
Corresponding to flashrom svn r281 and coreboot v2 svn r3397.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-06-29 10:57:13 +00:00
Peter Stuge
7e2c079367 Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.

Also fixes a build error in ichspi.c with gcc 4.2.2.

Corresponding to flashrom svn r280 and coreboot v2 svn r3395.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-06-29 01:30:41 +00:00
Stefan Reinauer
a9424d597d Multiple unrelated changes
* ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)

Corresponding to flashrom svn r278 and coreboot v2 svn r3393.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
2008-06-27 16:28:34 +00:00
Stefan Reinauer
325b5d47d8 Indent according to development guidelines
Corresponding to flashrom svn r277 and coreboot v2 svn r3392.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-06-27 15:18:20 +00:00
Dominik Geyer
b46acba6e0 Add support for SPI chips on ICH9
This is done by using the generic SPI interface.

Corresponding to flashrom svn r239 and coreboot v2 svn r3325.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-05-16 12:55:55 +00:00