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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-28 15:33:42 +02:00

53 Commits

Author SHA1 Message Date
Carl-Daniel Hailfinger
03adbe1269 Refine handling of spi_write_enable() failures to fix chip erases on ichspi
Until the ICH SPI driver can handle preopcodes as standalone opcodes,
we should handle such special opcode failure gracefully on ICH and
compatible chipsets.

This fixes chip erase on almost all ICH+VIA SPI masters.

Thanks to Ali Nadalizadeh for helping track down this bug!

Corresponding to flashrom svn r484.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2009-05-09 02:09:45 +00:00
Uwe Hermann
7b2969be53 Some coding style and consistency fixes
Corresponding to flashrom svn r429 and coreboot v2 svn r4117.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2009-04-15 10:52:49 +00:00
Peter Stuge
bf196e9199 Winbond SuperIO SPI driver
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!

Corresponding to flashrom svn r404 and coreboot v2 svn r3910.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
2009-01-26 03:08:45 +00:00