Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the
change from the chromium flashrom repo SHA
6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)
The rationale from that change was:
The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but
both chips identify in the same manner. Add GD25LQ128D to the name
of the part so that it doesn't confused people.
Making this name consistent will simplify further merging from the
chromium fork.
Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The N25Q is a stacked device, so it requires 0xC4 to perform a die
erase.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q
is almost entirely backwards compatible with the N25Q series, however,
the MT25Q has additional subsector erase commands available, and there
are differences in stacked devices in the higher capacity variants. The
N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q
devices are set with "Micron" as the vendor.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The AMD Am29F010 was marked TEST_OK_PRE in chromium repo change
SHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other
differences in the definition of this chip.
This is the only change from the Chromium repo to be upstreamed for AMD
chips.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34534
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Intel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their
SHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork
and here in upstream are otherwise substantially similar.
There are no other downstream changes for Intel chips to be upstreamed.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34533
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As per comments on https://review.coreboot.org/c/flashrom/+/33833/, make
placement of spaces in .tested attributes with literal definitions
consistent.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I18118f9f1e858547170fda8412bf6769f5cdcf53
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
For self-consistency, and to allow tools to assist with merging the
chromium fork of flashrom, sort the entries of flashchips.c. The file is
already largely sorted, though deviations have crept in over time.
This is a non-clever mostly ASCII-order sorting. It is not intended to
be permanent.
Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33931
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow automated tools to manipulate flashchips.c, make the definition
of SFDP-capable chip more consistent with other definitions. This
involves
- reordering fields to match both other entries and the definition of
struct flashchip.
- reformatting comments to make them consistent with other entries.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
For consistency, move a comment about an entry from inside the open
brace to outside it.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
For consistency and in order to allow automated tools to work with
flashchips.c, put fields in the same order as they are defined in struct
flashchip, in flash.h
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
To allow automated tools to manipulate flashchips.c, ensure that every
voltage attribute ends with a comma, even if it is the last member in
the definition.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The definition for the AT26DF321 has been commented out since it was
first added in 2008. The chip now appears to be obsolete, being marked
"obsolete" and unstocked at Digikey. It is also only referred to in
historical documents on the manufacturer's website (microchip.com).
To avoid further bitrot of this dead code, drop it.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
To allow automated tools to manipulate flashchips.c, ensure all
.block_erasers definitions have consistent formatting:
- start with the opening brace on a new line.
- ensure end brace indented exactly two tabs.
SFDP-capable chip is the one exception to this rule as it has an empty
block instead.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33831
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow automated tools to manipulate flashchips.c, make end of line
comment formatting more consistent. Specifically, this change moves the
comma from end of line to immediately after the field value, before the
commment.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Replace the single instance where a vendor name was spelled
inconsistently.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6478bc29f640f789f3b35e7b4816133f4a0d292e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33829
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For consistency, and to make the file amenable to manipulation by tools,
use only tabs when indenting. Some previous changes had introduced
spaces for indenting.
Also ensure that every table entry is separated by a single blank line.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib2193798cc52641d6c443f8851903c749b31cb74
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33828
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a 256Kb part with support for JEDEC 4 byte addressing modes.
Tested successfully for probe/read.
Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c
Signed-off-by: David Tomaschik <davidtomaschik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per user `The_Raven Raven` on the mailing list. Since the added
values had some inconsistencies, the chips are marked as untested.
Change-Id: I6c26aafdca232110986334e85297d73d513600dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Similar to W25Q256FV, but it supports the native 4BA page program
instruction (12h). Note that the variant with QE enabled by default
shares the device ID of the W25Q256FV.
Tested using a Raspberry Pi.
Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/29305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Port the code from chromeos flashrom.
Tested using W25Q128JVSIM in SPI mode.
Change-Id: I38397a0c831407afa21cddca8485664576fce92c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The IS25WP064 was tested successfully by Simon Buhrow as reported on
2018-9-4. While we are at it, also add the 32Mbit version which shares
the datasheet (as does the already supported 128Mbit version).
Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
4BA mode is entered by setting bit 7 for the extended address register.
Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
As per `The_Raven Raven` on the mailing list.
The tested chip was `W25Q40.W`, but it was later renamed to `W25Q40BW`
when the `W25Q40EW` was added.
Change-Id: I624adef2c5b4dd83f0ce93d6069e315fc407db19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Tomasz Walach on the mailing list.
Change-Id: Ib0d7485c7221f92ec13995c58065a48e08f57cd8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Stefan Szwarnowski on the mailing list.
Change-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Richard Hughes via the mailing list.
Change-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Konstantin on 2018-06-08 via mailing list.
Change-Id: I75fb4b17cf330451489811ae9303cbb33ebcb183
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As reported by David Martinka on the mailing list.
Erase has not been tested, but since writes are reported as working, it
is very likely erase works as well.
Change-Id: I172453fe902ccface2a3a85817d775d45dd7cf80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Alexander reported this chip as tested using a GD25B128CPIG (same device
ID, apparently) on 2018-08-30 via the mailing list. The chip name is
updated as well.
Change-Id: I134d3816c0f02e20764ab132a01bcba9f4e93f0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Grabbed from mailing list, created by Simon Buhrow. Since no logs were
attached, the chip is marked as untested.
Change-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
