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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-28 15:33:42 +02:00

6 Commits

Author SHA1 Message Date
Nico Huber
7e4968525d programmer: Smoothen register_spi_master() API
It was impossible to register a const struct spi_master that would
point to dynamically allocated `data`. Fix that so that we won't
have to create more mutable globals.

Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-13 14:37:29 +00:00
Anastasia Klimchuk
2348b18a5e digilent_spi.c: Refactor singleton states into reentrant pattern
Move global singleton states into a struct and store within
the spi_master data field for the life-time of the driver.

This is one of the steps on the way to move spi_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".

BUG=b:185191942
TEST=builds

Change-Id: I91b842913d4402a4a1bec896f19c2fe1f34772b1
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-05-12 23:19:15 +00:00
Edward O'Callaghan
e4ddc36371 const'ify flashctx to align signatures with cros flashrom
The ChromiumOS flashrom fork has since const'ify flashctx
in a few places. This aligns the function signatures to
match with downstream to ease forward porting patches
out of downstream back into mainline flashrom.

This patch is minimum viable alignment and so feedback is
welcome.

Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30 08:00:41 +00:00
Nico Huber
deeac7e41a spi: Drop spi_controller type
Not needed anymore. Drop it fast before it encourages anyone to
violate layers again!

Change-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33651
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-27 10:25:15 +00:00
Arthur Heymans
f3ce951fb3 digilent_spi: Avoid deprecated libusb functions
libusb 1.0.22 marked libusb_set_debug as deprecated. For such versions of
libusb, use libusb_set_option instead.

Change-Id: Ie139de36f15c4f4d87787cab0f968a2f0e6f0c8c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-31 20:45:52 +00:00
Lubomir Rintel
b2154e8a1d digilent_spi: add a driver for the iCEblink40 development board
This is driver that supports the Lattice iCE40 evaluation kits. On the
board is a SPI flash memory chip labeled ST 25P10VP.

Tested to work read/write/erase with "-p digilent_spi -c M25P10" or
with a patch that resets the part beforehands (in which case it gets
detected as a M25P10-A and is way faster due to paged writes).

Change-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-26 10:02:38 +00:00