3 Commits

Author	SHA1	Message	Date
Edward O'Callaghan	94991d83e4	lspcon_i2c_spi.c: Trivial style fix ... Change-Id: I0675b467d7b0d24626a336033668bf80bfeeb815 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>	2020-04-24 11:52:59 +00:00
Edward O'Callaghan	a25c13cdb6	lspcon_i2c_spi.c: Clean up some unnecessary indirection ... Clean up some confusion of implicit copies by indirection. This allows the caller of register_spi_master() to have it's internal state in the expected way. Also add an error when the mpu reset fails on init. BUG=b:148746232,b:153027771,b:140394053 BRANCH=none TEST=builds Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I66ba4ffeb696309b8ad5b5ba58650630e8feefa9 Reviewed-on: https://review.coreboot.org/c/flashrom/+/40470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>	2020-04-19 12:17:54 +00:00
Shiyu Sun	13a2ef6cbd	lspcon_i2c_spi.c: Add SPI-master support for PS17{5,6} ... This adds support for the Parade lspcon usb-c to HDMI protocol translater part that is i2c-controlled. The support allows the host to reach the SPI ROM that hangs off the part where it stores its firmware. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. BUG=b:148746232 BRANCH=none TEST=tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>	2020-04-01 06:34:16 +00:00