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The doc converted from https://wiki.flashrom.org/MSI_JSPI1 Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599 Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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=========
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MSI JSPI1
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=========
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JSPI1 is a 5x2 or 6x2 2.0mm pitch pin header on many MSI motherboards.
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It is used to recover from bad boot ROM images. Specifically,
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it appears to be used to connect an alternate ROM with a working image.
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Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another
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SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection.
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Some boards use 1.8V flash chips, while others use 3.3V flash chips;
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Check the flash chip datasheet to determine the correct value.
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**JSPI1 (5x2)**
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======== ======== ======== ====
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name pin pin name
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======== ======== ======== ====
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VCC 1 2 VCC
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MISO 3 4 MOSI
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#SS 5 6 SCLK
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GND 7 8 GND
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#HOLD 9 10 NC
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======== ======== ======== ====
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**JSPI1 (6x2)**
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======== ======== ======== ============
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name pin pin name
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======== ======== ======== ============
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VCC 1 2 VCC
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SO 3 4 SI
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#SS 5 6 CLK
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GND 7 8 GND
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NC 9 10 NC (no pin)
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#WP 11 12 #HOLD
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======== ======== ======== ============
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======== =====================================
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name function
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======== =====================================
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VCC Voltage (See flash chip datasheet)
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MISO SPI Master In/Slave Out
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MOSI SPI Master Out/Slave In
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#SS SPI Slave (Chip) Select (active low)
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SCLK SPI Clock
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GND ground/common
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#HOLD SPI hold (active low)
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#WP SPI write-protect (active low)
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NC Not Connected (or no pin)
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======== =====================================
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