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90286fe643
DJGPP for compiling DOS has other sizes for the normal int types and therefore throwing errors when using %i %d or %x with uint32_t. Fix these warnings by using the macros created for it and provided in inttypes.h. Change-Id: Ia75b6df981ce60c891161fe553c7ceab8570178d Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73040 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
148 lines
4.4 KiB
C
148 lines
4.4 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdbool.h>
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#include <stdlib.h>
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#include <string.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess_physmap.h"
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#include "platform/pci.h"
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#define PCI_VENDOR_ID_NVIDIA 0x10de
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/* Mask to restrict flash accesses to a 128kB memory window.
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* FIXME: Is this size a one-fits-all or card dependent?
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*/
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#define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
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#define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
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#define REG_FLASH_ACCESS 0x50
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#define BIT_FLASH_ACCESS BIT(0)
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struct gfxnvidia_data {
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struct pci_dev *dev;
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uint8_t *bar;
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uint32_t flash_access;
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};
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static const struct dev_entry gfx_nvidia[] = {
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{0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
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{0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
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{0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
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{0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
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{0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
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{0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
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{0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
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{0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
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{0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
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{0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
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{0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
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{0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
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{0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
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{0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
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{0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
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{0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
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{0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
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{0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
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{0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
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{0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
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{0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
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{0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
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{0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
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{0},
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};
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static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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const struct gfxnvidia_data *data = flash->mst->par.data;
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pci_mmio_writeb(val, data->bar + (addr & GFXNVIDIA_MEMMAP_MASK));
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}
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static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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const struct gfxnvidia_data *data = flash->mst->par.data;
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return pci_mmio_readb(data->bar + (addr & GFXNVIDIA_MEMMAP_MASK));
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}
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static int gfxnvidia_shutdown(void *par_data)
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{
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struct gfxnvidia_data *data = par_data;
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/* Restore original flash interface access state. */
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pci_write_long(data->dev, REG_FLASH_ACCESS, data->flash_access);
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free(par_data);
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return 0;
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}
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static const struct par_master par_master_gfxnvidia = {
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.chip_readb = gfxnvidia_chip_readb,
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.chip_writeb = gfxnvidia_chip_writeb,
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.shutdown = gfxnvidia_shutdown,
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};
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static int gfxnvidia_init(const struct programmer_cfg *cfg)
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{
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struct pci_dev *dev = NULL;
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uint32_t reg32;
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uint8_t *bar;
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dev = pcidev_init(cfg, gfx_nvidia, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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if (!io_base_addr)
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return 1;
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io_base_addr += 0x300000;
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msg_pinfo("Detected NVIDIA I/O base address: 0x%"PRIx32".\n", io_base_addr);
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bar = rphysmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
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if (bar == ERROR_PTR)
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return 1;
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struct gfxnvidia_data *data = calloc(1, sizeof(*data));
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if (!data) {
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msg_perr("Unable to allocate space for PAR master data\n");
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return 1;
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}
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data->dev = dev;
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data->bar = bar;
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/* Allow access to flash interface (will disable screen). */
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data->flash_access = pci_read_long(dev, REG_FLASH_ACCESS);
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reg32 = data->flash_access & ~BIT_FLASH_ACCESS;
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pci_write_long(dev, REG_FLASH_ACCESS, reg32);
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/* Write/erase doesn't work. */
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programmer_may_write = false;
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return register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, data);
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}
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const struct programmer_entry programmer_gfxnvidia = {
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.name = "gfxnvidia",
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.type = PCI,
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.devs.dev = gfx_nvidia,
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.init = gfxnvidia_init,
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};
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