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1d3a2fefbc
Convert all PCI-based external programmers to use special little-endian accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_ prefix for the abstraction layer. NOTE to package maintainers: With this patch, compilation and usage of flashrom should be safe on x86, x86_64, MIPS (little and big endian) and PowerPC (big endian). The internal programmer is disabled on non-x86/x86_64 (but it compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be compiled on non-x86/x86_64 because port space I/O is not (yet) supported. Please compile with default settings on x86/x86_64 and with the following settings on all other architectures: make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no CONFIG_RAYER_SPI=no Corresponding to flashrom svn r1111. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com>
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Joerg Fischer <turboj@web.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include "flash.h"
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#define PCI_VENDOR_ID_DRKAISER 0x1803
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#define PCI_MAGIC_DRKAISER_ADDR 0x50
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#define PCI_MAGIC_DRKAISER_VALUE 0xa971
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/* Mask to restrict flash accesses to the 128kB memory window. */
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#define DRKAISER_MEMMAP_MASK ((1 << 17) - 1)
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const struct pcidev_status drkaiser_pcidev[] = {
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{0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"},
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{},
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};
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static uint8_t *drkaiser_bar;
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int drkaiser_init(void)
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{
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uint32_t addr;
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get_io_perms();
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addr = pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2,
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drkaiser_pcidev);
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/* Write magic register to enable flash write. */
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pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR,
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PCI_MAGIC_DRKAISER_VALUE);
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/* Map 128KB flash memory window. */
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drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
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addr, 128 * 1024);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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return 0;
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}
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int drkaiser_shutdown(void)
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{
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/* Write protect the flash again. */
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pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, 0);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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};
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void drkaiser_chip_writeb(uint8_t val, chipaddr addr)
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{
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pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
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}
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uint8_t drkaiser_chip_readb(const chipaddr addr)
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{
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return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
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}
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