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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-26 22:52:34 +02:00
flashrom/physmap.c
Stefan Tauner 0554ca5cd3 Add a bunch of new/tested stuff and various small changes 18
Tested mainboards:
OK:
 - ASUS C60M1-I
   http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html
 - ASUS P8H77-I
   http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html
 - ASUS P8H77-M
   http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html
 - ASUS P8P67 LE (B2)
   http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html
 - Elitegroup GeForce6100PM-M2 (V3.0)
   http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html
 - GIGABYTE GA-P55A-UD7
   http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html
 - MSI B75MA-E33 (MS-7808)
   http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html
 - MSI H77MA-G43 (MS-7756)
   http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html
 - MSI KA780G (MS-7551)
   http://paste.flashrom.org/view.php?id=1617
 - SAPPHIRE IPC-E350M1
   Reported by xvilka on IRC
 - Supermicro X8DTG-D
   http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html
NOT OK:
 - ASRock Fatal1ty Z77 Performance
   http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html
 - ASRock Z68 Extreme4
   http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html
 - ASUS P8B75-M LE
   http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html
 - ASUS P8P67-M PRO
   http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html
 - ASUS P8Z68-V LE
   http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html
 - Intel DQ77MK
   http://paste.flashrom.org/view.php?id=1603
 - Supermicro X9DRD-7LN4F
   http://paste.flashrom.org/view.php?id=1582
 - Supermicro X9SCE-F
   http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html
 - Supermicro X9SCM-F
   http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html
 - Tyan S7066
   http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html

Chipsets:
 - Marked Intel B75 as tested
   http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html
 - Marked Intel H77 as tested
   http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html
 - Removed 10de:03e2 because it is apparently the MCP61 host bridge.
   It was reclassified to Host Bridge in the PCI device ID database and there
   is at least one report suggesting this configuration too:
   http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html
 - Added MCP89 which hopefully works with the code for previous versions.
   Thanks to James Laird for submitting this change.

Tested flash chips:
 - Atmel AT25DF641(A) to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html
 - Atmel AT25F512 to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html
   Also, change its ID according to Modification of PCN SC040401A:
   "There has been a change in the returned value of the Product Identification
   (RDID) command, the AT25F512A RDID code is 65h compared to 60h from
   the AT25F512 product."
   It seems to be quite likely that all AT25F512 are fully functional relabeled
   AT25F1024 chips. There are even some hints in the datasheet:
   in table 6 they stress that address pin 16 needs to be low under all circum-
   stances; while continuous reads can wrap around on the AT25F1024 the DS
   notes "For the AT25F512, the read command must be terminated when the
   highest address (00FFFF) is reached." OTOH the lock bit semantics are
   different, but this has not been tested thoroughly
 - Atmel AT25F512A to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1569
 - Eon EN25F05 to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1571
 - Macronix MX25L12805(D) to PREW (+REW)
   http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html
 - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P)
   Tested by Stefan Tauner
 - Micron/Numonyx/ST M25PX80 to PREW (+PREW)
   Tested by Stefan Tauner
 - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW)
   Tested by Stefan Tauner
 - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P)
   Tested by Stefan Tauner
 - SST SST25VF040B to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1574
 - SST SST25VF040B.REMS to PREW (+EW)
   http://paste.flashrom.org/view.php?id=1575
 - ST M25P05-A to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1576
 - ST M29W512B to PREW (+W)
   http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html
 - Winbond W25Q64.W to PREW (+PREW)
   Tested by the chromiumos guys.
 - Winbond W25Q128.V to PREW (+REW)
   http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html
 - Winbond W25X20 to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html

Miscellaneous:
 - Add Lenovo X201 to the laptop whitelist.
 - Add chip IDs for the ESMT F25L..QA family.
 - Add chip IDs for a few Macronix MX25 models.
 - The list of flashchips is not sorted strictly alphabetically and should not be
   either. Refine the comment explaining the scheme on top of the list.
 - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb).
 - Use z length modifier in (more) prints for size_t types.
 - Remove chips >16MB again because our current implementation of memory mapping
   the flash chip violates common rules by mapping a window as large as the chip.
   This leads to failing mmaps as can be seen here:
   http://paste.flashrom.org/view.php?id=1695
 - Document spispeed parameter of linux_spi (and fix some leaks).
 - Rephrase the "multiple chips detected" message because it was confusing.
 - Skip verification step if the image is equal to the flash contents.
 - Tiny other stuff.

Corresponding to flashrom svn r1702.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2013-07-25 22:54:25 +00:00

599 lines
13 KiB
C

/*
* This file is part of the flashrom project.
*
* Copyright (C) 2009 Peter Stuge <peter@stuge.se>
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2010 Carl-Daniel Hailfinger
* Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include "flash.h"
#include "hwaccess.h"
#if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__)
/* No file access needed/possible to get mmap access permissions or access MSR. */
#include <sys/stat.h>
#include <fcntl.h>
#endif
#ifdef __DJGPP__
#include <dpmi.h>
#include <sys/nearptr.h>
#define MEM_DEV "dpmi"
static void *realmem_map;
static void *map_first_meg(uintptr_t phys_addr, size_t len)
{
if (realmem_map)
return realmem_map + phys_addr;
realmem_map = valloc(1024 * 1024);
if (!realmem_map)
return ERROR_PTR;
if (__djgpp_map_physical_memory(realmem_map, (1024 * 1024), 0)) {
free(realmem_map);
realmem_map = NULL;
return ERROR_PTR;
}
return realmem_map + phys_addr;
}
static void *sys_physmap(uintptr_t phys_addr, size_t len)
{
int ret;
__dpmi_meminfo mi;
/* Enable 4GB limit on DS descriptor. */
if (!__djgpp_nearptr_enable())
return ERROR_PTR;
if ((phys_addr + len - 1) < (1024 * 1024)) {
/* We need to use another method to map first 1MB. */
return map_first_meg(phys_addr, len);
}
mi.address = phys_addr;
mi.size = len;
ret = __dpmi_physical_address_mapping(&mi);
if (ret != 0)
return ERROR_PTR;
return (void *) mi.address + __djgpp_conventional_base;
}
#define sys_physmap_rw_uncached sys_physmap
#define sys_physmap_ro_cached sys_physmap
void physunmap(void *virt_addr, size_t len)
{
__dpmi_meminfo mi;
/* There is no known way to unmap the first 1 MB. The DPMI server will
* do this for us on exit.
*/
if ((virt_addr >= realmem_map) &&
((virt_addr + len) <= (realmem_map + (1024 * 1024)))) {
return;
}
mi.address = (unsigned long) virt_addr;
__dpmi_free_physical_address_mapping(&mi);
}
#elif defined(__LIBPAYLOAD__)
#include <arch/virtual.h>
#define MEM_DEV ""
void *sys_physmap(uintptr_t phys_addr, size_t len)
{
return (void *)phys_to_virt(phys_addr);
}
#define sys_physmap_rw_uncached sys_physmap
#define sys_physmap_ro_cached sys_physmap
void physunmap(void *virt_addr, size_t len)
{
}
#elif defined(__MACH__) && defined(__APPLE__)
#define MEM_DEV "DirectHW"
static void *sys_physmap(uintptr_t phys_addr, size_t len)
{
/* The short form of ?: is a GNU extension.
* FIXME: map_physical returns NULL both for errors and for success
* if the region is mapped at virtual address zero. If in doubt, report
* an error until a better interface exists.
*/
return map_physical(phys_addr, len) ? : ERROR_PTR;
}
/* The OS X driver does not differentiate between mapping types. */
#define sys_physmap_rw_uncached sys_physmap
#define sys_physmap_ro_cached sys_physmap
void physunmap(void *virt_addr, size_t len)
{
unmap_physical(virt_addr, len);
}
#else
#include <sys/mman.h>
#if defined (__sun) && (defined(__i386) || defined(__amd64))
# define MEM_DEV "/dev/xsvc"
#else
# define MEM_DEV "/dev/mem"
#endif
static int fd_mem = -1;
static int fd_mem_cached = -1;
/* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */
static void *sys_physmap_rw_uncached(uintptr_t phys_addr, size_t len)
{
void *virt_addr;
if (-1 == fd_mem) {
/* Open the memory device UNCACHED. Important for MMIO. */
if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) {
msg_perr("Critical error: open(" MEM_DEV "): %s\n", strerror(errno));
exit(2);
}
}
virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED,
fd_mem, (off_t)phys_addr);
return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr;
}
/* For reading DMI/coreboot/whatever tables. We should never write, and we
* do not care about caching.
*/
static void *sys_physmap_ro_cached(uintptr_t phys_addr, size_t len)
{
void *virt_addr;
if (-1 == fd_mem_cached) {
/* Open the memory device CACHED. */
if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) {
msg_perr("Critical error: open(" MEM_DEV "): %s\n", strerror(errno));
exit(2);
}
}
virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED,
fd_mem_cached, (off_t)phys_addr);
return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr;
}
void physunmap(void *virt_addr, size_t len)
{
if (len == 0) {
msg_pspew("Not unmapping zero size at %p\n", virt_addr);
return;
}
munmap(virt_addr, len);
}
#endif
#define PHYSMAP_NOFAIL 0
#define PHYSMAP_MAYFAIL 1
#define PHYSMAP_RW 0
#define PHYSMAP_RO 1
static void *physmap_common(const char *descr, uintptr_t phys_addr,
size_t len, int mayfail, int readonly)
{
void *virt_addr;
if (len == 0) {
msg_pspew("Not mapping %s, zero size at 0x%0*" PRIxPTR ".\n", descr, PRIxPTR_WIDTH, phys_addr);
return ERROR_PTR;
}
if ((getpagesize() - 1) & len) {
msg_perr("Mapping %s at 0x%0*" PRIxPTR ", unaligned size 0x%zx.\n",
descr, PRIxPTR_WIDTH, phys_addr, len);
}
if ((getpagesize() - 1) & phys_addr) {
msg_perr("Mapping %s, 0x%zx bytes at unaligned 0x%0*" PRIxPTR ".\n",
descr, len, PRIxPTR_WIDTH, phys_addr);
}
if (readonly)
virt_addr = sys_physmap_ro_cached(phys_addr, len);
else
virt_addr = sys_physmap_rw_uncached(phys_addr, len);
if (ERROR_PTR == virt_addr) {
if (NULL == descr)
descr = "memory";
msg_perr("Error accessing %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n",
descr, len, PRIxPTR_WIDTH, phys_addr);
msg_perr(MEM_DEV " mmap failed: %s\n", strerror(errno));
#ifdef __linux__
if (EINVAL == errno) {
msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n");
msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n");
msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n");
msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n");
msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n");
}
#elif defined (__OpenBSD__)
msg_perr("Please set securelevel=-1 in /etc/rc.securelevel "
"and reboot, or reboot into\n"
"single user mode.\n");
#endif
if (!mayfail)
exit(3);
}
return virt_addr;
}
void *physmap(const char *descr, uintptr_t phys_addr, size_t len)
{
return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL,
PHYSMAP_RW);
}
void *physmap_try_ro(const char *descr, uintptr_t phys_addr, size_t len)
{
return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL,
PHYSMAP_RO);
}
/* MSR abstraction implementations for Linux, OpenBSD, FreeBSD/Dragonfly, OSX, libpayload
* and a non-working default implemenation on the bottom. See also hwaccess.h for some (re)declarations. */
#if defined(__i386__) || defined(__x86_64__)
#ifdef __linux__
/*
* Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
* which are ring0 privileged instructions so only the kernel can do the
* read/write. This function, therefore, requires that the msr kernel module
* be loaded to access these instructions from user space using device
* /dev/cpu/0/msr.
*/
static int fd_msr = -1;
msr_t rdmsr(int addr)
{
uint32_t buf[2];
msr_t msr = { 0xffffffff, 0xffffffff };
if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
msg_perr("Could not lseek() MSR: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
if (read(fd_msr, buf, 8) == 8) {
msr.lo = buf[0];
msr.hi = buf[1];
return msr;
}
if (errno != EIO) {
// A severe error.
msg_perr("Could not read() MSR: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
return msr;
}
int wrmsr(int addr, msr_t msr)
{
uint32_t buf[2];
buf[0] = msr.lo;
buf[1] = msr.hi;
if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
msg_perr("Could not lseek() MSR: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
if (write(fd_msr, buf, 8) != 8 && errno != EIO) {
msg_perr("Could not write() MSR: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
/* Some MSRs must not be written. */
if (errno == EIO)
return -1;
return 0;
}
int setup_cpu_msr(int cpu)
{
char msrfilename[64];
memset(msrfilename, 0, sizeof(msrfilename));
snprintf(msrfilename, sizeof(msrfilename), "/dev/cpu/%d/msr", cpu);
if (fd_msr != -1) {
msg_pinfo("MSR was already initialized\n");
return -1;
}
fd_msr = open(msrfilename, O_RDWR);
if (fd_msr < 0) {
msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno));
msg_pinfo("Did you run 'modprobe msr'?\n");
return -1;
}
return 0;
}
void cleanup_cpu_msr(void)
{
if (fd_msr == -1) {
msg_pinfo("No MSR initialized.\n");
return;
}
close(fd_msr);
/* Clear MSR file descriptor. */
fd_msr = -1;
}
#elif defined(__OpenBSD__) /* This does only work for certain AMD Geode LX systems see amdmsr(4). */
#include <sys/ioctl.h>
#include <machine/amdmsr.h>
static int fd_msr = -1;
msr_t rdmsr(int addr)
{
struct amdmsr_req args;
msr_t msr = { 0xffffffff, 0xffffffff };
args.addr = (uint32_t)addr;
if (ioctl(fd_msr, RDMSR, &args) < 0) {
msg_perr("Error while executing RDMSR ioctl: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
msr.lo = args.val & 0xffffffff;
msr.hi = args.val >> 32;
return msr;
}
int wrmsr(int addr, msr_t msr)
{
struct amdmsr_req args;
args.addr = addr;
args.val = (((uint64_t)msr.hi) << 32) | msr.lo;
if (ioctl(fd_msr, WRMSR, &args) < 0) {
msg_perr("Error while executing WRMSR ioctl: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
return 0;
}
int setup_cpu_msr(int cpu)
{
char msrfilename[64];
memset(msrfilename, 0, sizeof(msrfilename));
snprintf(msrfilename, sizeof(msrfilename), "/dev/amdmsr");
if (fd_msr != -1) {
msg_pinfo("MSR was already initialized\n");
return -1;
}
fd_msr = open(msrfilename, O_RDWR);
if (fd_msr < 0) {
msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno));
return -1;
}
return 0;
}
void cleanup_cpu_msr(void)
{
if (fd_msr == -1) {
msg_pinfo("No MSR initialized.\n");
return;
}
close(fd_msr);
/* Clear MSR file descriptor. */
fd_msr = -1;
}
#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
#include <sys/ioctl.h>
typedef struct {
int msr;
uint64_t data;
} cpu_msr_args_t;
#define CPU_RDMSR _IOWR('c', 1, cpu_msr_args_t)
#define CPU_WRMSR _IOWR('c', 2, cpu_msr_args_t)
static int fd_msr = -1;
msr_t rdmsr(int addr)
{
cpu_msr_args_t args;
msr_t msr = { 0xffffffff, 0xffffffff };
args.msr = addr;
if (ioctl(fd_msr, CPU_RDMSR, &args) < 0) {
msg_perr("Error while executing CPU_RDMSR ioctl: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
msr.lo = args.data & 0xffffffff;
msr.hi = args.data >> 32;
return msr;
}
int wrmsr(int addr, msr_t msr)
{
cpu_msr_args_t args;
args.msr = addr;
args.data = (((uint64_t)msr.hi) << 32) | msr.lo;
if (ioctl(fd_msr, CPU_WRMSR, &args) < 0) {
msg_perr("Error while executing CPU_WRMSR ioctl: %s\n", strerror(errno));
close(fd_msr);
exit(1);
}
return 0;
}
int setup_cpu_msr(int cpu)
{
char msrfilename[64];
memset(msrfilename, 0, sizeof(msrfilename));
snprintf(msrfilename, sizeof(msrfilename), "/dev/cpu%d", cpu);
if (fd_msr != -1) {
msg_pinfo("MSR was already initialized\n");
return -1;
}
fd_msr = open(msrfilename, O_RDWR);
if (fd_msr < 0) {
msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno));
msg_pinfo("Did you install ports/sysutils/devcpu?\n");
return -1;
}
return 0;
}
void cleanup_cpu_msr(void)
{
if (fd_msr == -1) {
msg_pinfo("No MSR initialized.\n");
return;
}
close(fd_msr);
/* Clear MSR file descriptor. */
fd_msr = -1;
}
#elif defined(__MACH__) && defined(__APPLE__)
/* rdmsr() and wrmsr() are provided by DirectHW which needs neither setup nor cleanup. */
int setup_cpu_msr(int cpu)
{
// Always succeed for now
return 0;
}
void cleanup_cpu_msr(void)
{
// Nothing, yet.
}
#elif defined(__LIBPAYLOAD__)
msr_t libpayload_rdmsr(int addr)
{
msr_t msr;
unsigned long long val = _rdmsr(addr);
msr.lo = val & 0xffffffff;
msr.hi = val >> 32;
return msr;
}
int libpayload_wrmsr(int addr, msr_t msr)
{
_wrmsr(addr, msr.lo | ((unsigned long long)msr.hi << 32));
return 0;
}
int setup_cpu_msr(int cpu)
{
return 0;
}
void cleanup_cpu_msr(void)
{
}
#else
/* default MSR implementation */
msr_t rdmsr(int addr)
{
msr_t ret = { 0xffffffff, 0xffffffff };
return ret;
}
int wrmsr(int addr, msr_t msr)
{
return -1;
}
int setup_cpu_msr(int cpu)
{
msg_pinfo("No MSR support for your OS yet.\n");
return -1;
}
void cleanup_cpu_msr(void)
{
// Nothing, yet.
}
#endif // OS switches for MSR code
#else // x86
/* Does MSR exist on non-x86 architectures? */
#endif // arch switches for MSR code