mirror of
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a8d838d9d3
The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Corresponding to flashrom svn r1460. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
249 lines
6.3 KiB
C
249 lines
6.3 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
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* Copyright (c) 2011 Stefan Tauner
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#ifndef __ICH_DESCRIPTORS_H__
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#define __ICH_DESCRIPTORS_H__ 1
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#include <stdint.h>
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#include "programmer.h" /* for enum ich_chipset */
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/* FIXME: Replace with generic return codes */
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#define ICH_RET_OK 0
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#define ICH_RET_ERR -1
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#define ICH_RET_WARN -2
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#define ICH_RET_PARAM -3
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#define ICH_RET_OOB -4
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#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */
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/* 0-1: reserved */
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#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */
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#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF)
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#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */
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#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF)
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/* 15-31: reserved */
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#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */
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/* Field locations and semantics for LVSCC, UVSCC and related words in the flash
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* descriptor are equal therefore they all share the same macros below. */
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#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */
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#define VSCC_BES (0x3 << VSCC_BES_OFF)
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#define VSCC_WG_OFF 2 /* 2: Write Granularity */
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#define VSCC_WG (0x1 << VSCC_WG_OFF)
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#define VSCC_WSR_OFF 3 /* 3: Write Status Required */
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#define VSCC_WSR (0x1 << VSCC_WSR_OFF)
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#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */
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#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF)
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/* 5-7: reserved */
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#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */
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#define VSCC_EO (0xff << VSCC_EO_OFF)
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/* 16-22: reserved */
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#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */
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#define VSCC_VCL (0x1 << VSCC_VCL_OFF)
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/* 24-31: reserved */
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#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000)
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#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000)
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void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity);
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struct ich_desc_content {
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uint32_t FLVALSIG; /* 0x00 */
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union { /* 0x04 */
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uint32_t FLMAP0;
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struct {
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uint32_t FCBA :8, /* Flash Component Base Address */
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NC :2, /* Number Of Components */
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:6,
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FRBA :8, /* Flash Region Base Address */
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NR :3, /* Number Of Regions */
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:5;
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};
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};
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union { /* 0x08 */
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uint32_t FLMAP1;
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struct {
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uint32_t FMBA :8, /* Flash Master Base Address */
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NM :3, /* Number Of Masters */
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:5,
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FISBA :8, /* Flash ICH Strap Base Address */
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ISL :8; /* ICH Strap Length */
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};
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};
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union { /* 0x0c */
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uint32_t FLMAP2;
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struct {
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uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
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MSL :8, /* MCH Strap Length */
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:16;
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};
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};
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};
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struct ich_desc_component {
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union { /* 0x00 */
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uint32_t FLCOMP; /* Flash Components Register */
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struct {
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uint32_t comp1_density :3,
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comp2_density :3,
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:11,
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freq_read :3,
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fastread :1,
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freq_fastread :3,
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freq_write :3,
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freq_read_id :3,
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:2;
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};
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};
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union { /* 0x04 */
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uint32_t FLILL; /* Flash Invalid Instructions Register */
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struct {
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uint32_t invalid_instr0 :8,
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invalid_instr1 :8,
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invalid_instr2 :8,
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invalid_instr3 :8;
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};
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};
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union { /* 0x08 */
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uint32_t FLPB; /* Flash Partition Boundary Register */
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struct {
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uint32_t FPBA :13, /* Flash Partition Boundary Addr */
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:19;
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};
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};
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};
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struct ich_desc_region {
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union {
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uint32_t FLREGs[5];
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struct {
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struct { /* FLREG0 Flash Descriptor */
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uint32_t reg0_base :13,
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:3,
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reg0_limit :13,
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:3;
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};
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struct { /* FLREG1 BIOS */
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uint32_t reg1_base :13,
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:3,
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reg1_limit :13,
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:3;
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};
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struct { /* FLREG2 ME */
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uint32_t reg2_base :13,
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:3,
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reg2_limit :13,
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:3;
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};
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struct { /* FLREG3 GbE */
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uint32_t reg3_base :13,
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:3,
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reg3_limit :13,
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:3;
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};
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struct { /* FLREG4 Platform */
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uint32_t reg4_base :13,
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:3,
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reg4_limit :13,
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:3;
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};
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};
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};
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};
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struct ich_desc_master {
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union {
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uint32_t FLMSTR1;
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struct {
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uint32_t BIOS_req_ID :16,
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BIOS_descr_r :1,
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BIOS_BIOS_r :1,
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BIOS_ME_r :1,
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BIOS_GbE_r :1,
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BIOS_plat_r :1,
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:3,
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BIOS_descr_w :1,
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BIOS_BIOS_w :1,
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BIOS_ME_w :1,
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BIOS_GbE_w :1,
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BIOS_plat_w :1,
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:3;
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};
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};
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union {
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uint32_t FLMSTR2;
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struct {
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uint32_t ME_req_ID :16,
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ME_descr_r :1,
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ME_BIOS_r :1,
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ME_ME_r :1,
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ME_GbE_r :1,
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ME_plat_r :1,
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:3,
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ME_descr_w :1,
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ME_BIOS_w :1,
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ME_ME_w :1,
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ME_GbE_w :1,
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ME_plat_w :1,
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:3;
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};
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};
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union {
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uint32_t FLMSTR3;
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struct {
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uint32_t GbE_req_ID :16,
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GbE_descr_r :1,
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GbE_BIOS_r :1,
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GbE_ME_r :1,
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GbE_GbE_r :1,
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GbE_plat_r :1,
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:3,
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GbE_descr_w :1,
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GbE_BIOS_w :1,
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GbE_ME_w :1,
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GbE_GbE_w :1,
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GbE_plat_w :1,
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:3;
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};
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};
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};
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struct ich_descriptors {
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struct ich_desc_content content;
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struct ich_desc_component component;
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struct ich_desc_region region;
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struct ich_desc_master master;
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};
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void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc);
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void prettyprint_ich_descriptor_content(const struct ich_desc_content *content);
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void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc);
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void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc);
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void prettyprint_ich_descriptor_master(const struct ich_desc_master *master);
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int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc);
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int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx);
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#endif /* __ICH_DESCRIPTORS_H__ */
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#endif /* defined(__i386__) || defined(__x86_64__) */
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