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https://review.coreboot.org/flashrom.git
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26f7e64cb1
With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Corresponding to flashrom svn r727. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
1047 lines
26 KiB
C
1047 lines
26 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Contains the generic SPI framework
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*/
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#include <string.h>
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#include "flash.h"
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#include "flashchips.h"
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#include "spi.h"
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enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
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void *spibar = NULL;
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void spi_prettyprint_status_register(struct flashchip *flash);
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const struct spi_programmer spi_programmer[] = {
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{ /* SPI_CONTROLLER_NONE */
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.command = NULL,
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.multicommand = NULL,
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.read = NULL,
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.write_256 = NULL,
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},
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{ /* SPI_CONTROLLER_ICH7 */
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.command = ich_spi_send_command,
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.multicommand = ich_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_ICH9 */
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.command = ich_spi_send_command,
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.multicommand = ich_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_IT87XX */
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.command = it8716f_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = it8716f_spi_chip_read,
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.write_256 = it8716f_spi_chip_write_256,
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},
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{ /* SPI_CONTROLLER_SB600 */
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.command = sb600_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = sb600_spi_read,
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.write_256 = sb600_spi_write_1,
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},
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{ /* SPI_CONTROLLER_VIA */
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.command = ich_spi_send_command,
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.multicommand = ich_spi_send_multicommand,
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.read = ich_spi_read,
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.write_256 = ich_spi_write_256,
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},
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{ /* SPI_CONTROLLER_WBSIO */
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.command = wbsio_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = wbsio_spi_read,
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.write_256 = wbsio_spi_write_1,
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},
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#if FT2232_SPI_SUPPORT == 1
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{ /* SPI_CONTROLLER_FT2232 */
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.command = ft2232_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = ft2232_spi_read,
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.write_256 = ft2232_spi_write_256,
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},
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#endif
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#if DUMMY_SUPPORT == 1
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{ /* SPI_CONTROLLER_DUMMY */
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.command = dummy_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = NULL,
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.write_256 = NULL,
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},
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#endif
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{}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
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};
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const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
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int spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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if (!spi_programmer[spi_controller].command) {
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fprintf(stderr, "%s called, but SPI is unsupported on this "
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"hardware. Please report a bug.\n", __func__);
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return 1;
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}
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return spi_programmer[spi_controller].command(writecnt, readcnt,
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writearr, readarr);
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}
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int spi_send_multicommand(struct spi_command *cmds)
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{
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if (!spi_programmer[spi_controller].multicommand) {
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fprintf(stderr, "%s called, but SPI is unsupported on this "
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"hardware. Please report a bug.\n", __func__);
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return 1;
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}
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return spi_programmer[spi_controller].multicommand(cmds);
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}
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int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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struct spi_command cmd[] = {
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{
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.writecnt = writecnt,
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.readcnt = readcnt,
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.writearr = writearr,
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.readarr = readarr,
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}, {
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.writecnt = 0,
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.writearr = NULL,
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.readcnt = 0,
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.readarr = NULL,
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}};
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return spi_send_multicommand(cmd);
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}
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int default_spi_send_multicommand(struct spi_command *cmds)
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{
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int result = 0;
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for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
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result = spi_send_command(cmds->writecnt, cmds->readcnt,
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cmds->writearr, cmds->readarr);
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}
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return result;
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}
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static int spi_rdid(unsigned char *readarr, int bytes)
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{
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const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
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int ret;
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int i;
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ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
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if (ret)
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return ret;
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printf_debug("RDID returned");
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for (i = 0; i < bytes; i++)
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printf_debug(" 0x%02x", readarr[i]);
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printf_debug(". ");
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return 0;
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}
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static int spi_rems(unsigned char *readarr)
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{
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unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
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uint32_t readaddr;
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int ret;
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ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
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if (ret == SPI_INVALID_ADDRESS) {
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/* Find the lowest even address allowed for reads. */
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readaddr = (spi_get_valid_read_addr() + 1) & ~1;
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cmd[1] = (readaddr >> 16) & 0xff,
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cmd[2] = (readaddr >> 8) & 0xff,
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cmd[3] = (readaddr >> 0) & 0xff,
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ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
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}
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if (ret)
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return ret;
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printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]);
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return 0;
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}
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static int spi_res(unsigned char *readarr)
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{
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unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
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uint32_t readaddr;
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int ret;
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ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
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if (ret == SPI_INVALID_ADDRESS) {
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/* Find the lowest even address allowed for reads. */
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readaddr = (spi_get_valid_read_addr() + 1) & ~1;
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cmd[1] = (readaddr >> 16) & 0xff,
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cmd[2] = (readaddr >> 8) & 0xff,
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cmd[3] = (readaddr >> 0) & 0xff,
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ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
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}
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if (ret)
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return ret;
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printf_debug("RES returned %02x. ", readarr[0]);
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return 0;
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}
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int spi_write_enable(void)
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{
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const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
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int result;
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/* Send WREN (Write Enable) */
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result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
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if (result)
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fprintf(stderr, "%s failed\n", __func__);
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return result;
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}
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int spi_write_disable(void)
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{
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const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
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/* Send WRDI (Write Disable) */
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return spi_send_command(sizeof(cmd), 0, cmd, NULL);
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}
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static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
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{
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unsigned char readarr[4];
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uint32_t id1;
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uint32_t id2;
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if (spi_rdid(readarr, bytes))
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return 0;
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if (!oddparity(readarr[0]))
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printf_debug("RDID byte 0 parity violation. ");
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/* Check if this is a continuation vendor ID */
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if (readarr[0] == 0x7f) {
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if (!oddparity(readarr[1]))
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printf_debug("RDID byte 1 parity violation. ");
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id1 = (readarr[0] << 8) | readarr[1];
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id2 = readarr[2];
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if (bytes > 3) {
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id2 <<= 8;
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id2 |= readarr[3];
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}
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} else {
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id1 = readarr[0];
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id2 = (readarr[1] << 8) | readarr[2];
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}
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printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
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if (id1 == flash->manufacture_id && id2 == flash->model_id) {
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/* Print the status register to tell the
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* user about possible write protection.
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*/
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spi_prettyprint_status_register(flash);
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return 1;
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}
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/* Test if this is a pure vendor match. */
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if (id1 == flash->manufacture_id &&
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GENERIC_DEVICE_ID == flash->model_id)
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return 1;
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return 0;
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}
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int probe_spi_rdid(struct flashchip *flash)
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{
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return probe_spi_rdid_generic(flash, 3);
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}
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/* support 4 bytes flash ID */
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int probe_spi_rdid4(struct flashchip *flash)
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{
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/* only some SPI chipsets support 4 bytes commands */
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switch (spi_controller) {
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case SPI_CONTROLLER_ICH7:
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case SPI_CONTROLLER_ICH9:
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case SPI_CONTROLLER_VIA:
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case SPI_CONTROLLER_SB600:
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case SPI_CONTROLLER_WBSIO:
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#if FT2232_SPI_SUPPORT == 1
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case SPI_CONTROLLER_FT2232:
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#endif
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#if DUMMY_SUPPORT == 1
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case SPI_CONTROLLER_DUMMY:
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#endif
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return probe_spi_rdid_generic(flash, 4);
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default:
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printf_debug("4b ID not supported on this SPI controller\n");
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}
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return 0;
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}
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int probe_spi_rems(struct flashchip *flash)
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{
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unsigned char readarr[JEDEC_REMS_INSIZE];
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uint32_t id1, id2;
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if (spi_rems(readarr))
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return 0;
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id1 = readarr[0];
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id2 = readarr[1];
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printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
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if (id1 == flash->manufacture_id && id2 == flash->model_id) {
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/* Print the status register to tell the
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* user about possible write protection.
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*/
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spi_prettyprint_status_register(flash);
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return 1;
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}
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/* Test if this is a pure vendor match. */
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if (id1 == flash->manufacture_id &&
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GENERIC_DEVICE_ID == flash->model_id)
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return 1;
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return 0;
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}
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int probe_spi_res(struct flashchip *flash)
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{
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unsigned char readarr[3];
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uint32_t id2;
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/* Check if RDID was successful and did not return 0xff 0xff 0xff.
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* In that case, RES is pointless.
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*/
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if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) ||
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(readarr[1] != 0xff) || (readarr[2] != 0xff)))
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return 0;
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if (spi_res(readarr))
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return 0;
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id2 = readarr[0];
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printf_debug("%s: id 0x%x\n", __func__, id2);
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if (id2 != flash->model_id)
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return 0;
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/* Print the status register to tell the
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* user about possible write protection.
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*/
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spi_prettyprint_status_register(flash);
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return 1;
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}
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uint8_t spi_read_status_register(void)
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{
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const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
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/* FIXME: No workarounds for driver/hardware bugs in generic code. */
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unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
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int ret;
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/* Read Status Register */
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ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
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if (ret)
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fprintf(stderr, "RDSR failed!\n");
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return readarr[0];
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}
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/* Prettyprint the status register. Common definitions. */
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void spi_prettyprint_status_register_common(uint8_t status)
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{
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printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
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"%sset\n", (status & (1 << 5)) ? "" : "not ");
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printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
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"%sset\n", (status & (1 << 4)) ? "" : "not ");
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printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
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"%sset\n", (status & (1 << 3)) ? "" : "not ");
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printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
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"%sset\n", (status & (1 << 2)) ? "" : "not ");
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printf_debug("Chip status register: Write Enable Latch (WEL) is "
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"%sset\n", (status & (1 << 1)) ? "" : "not ");
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printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
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"%sset\n", (status & (1 << 0)) ? "" : "not ");
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}
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/* Prettyprint the status register. Works for
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* ST M25P series
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* MX MX25L series
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*/
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void spi_prettyprint_status_register_st_m25p(uint8_t status)
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{
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printf_debug("Chip status register: Status Register Write Disable "
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"(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
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printf_debug("Chip status register: Bit 6 is "
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"%sset\n", (status & (1 << 6)) ? "" : "not ");
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spi_prettyprint_status_register_common(status);
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}
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void spi_prettyprint_status_register_sst25(uint8_t status)
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{
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printf_debug("Chip status register: Block Protect Write Disable "
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"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
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printf_debug("Chip status register: Auto Address Increment Programming "
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"(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
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spi_prettyprint_status_register_common(status);
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}
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/* Prettyprint the status register. Works for
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* SST 25VF016
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*/
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void spi_prettyprint_status_register_sst25vf016(uint8_t status)
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{
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const char *bpt[] = {
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"none",
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"1F0000H-1FFFFFH",
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"1E0000H-1FFFFFH",
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"1C0000H-1FFFFFH",
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"180000H-1FFFFFH",
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"100000H-1FFFFFH",
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"all", "all"
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};
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spi_prettyprint_status_register_sst25(status);
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printf_debug("Resulting block protection : %s\n",
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bpt[(status & 0x1c) >> 2]);
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}
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void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
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{
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const char *bpt[] = {
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"none",
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"0x70000-0x7ffff",
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"0x60000-0x7ffff",
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"0x40000-0x7ffff",
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"all blocks", "all blocks", "all blocks", "all blocks"
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};
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spi_prettyprint_status_register_sst25(status);
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printf_debug("Resulting block protection : %s\n",
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bpt[(status & 0x1c) >> 2]);
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}
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void spi_prettyprint_status_register(struct flashchip *flash)
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{
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uint8_t status;
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status = spi_read_status_register();
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printf_debug("Chip status register is %02x\n", status);
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switch (flash->manufacture_id) {
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case ST_ID:
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if (((flash->model_id & 0xff00) == 0x2000) ||
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((flash->model_id & 0xff00) == 0x2500))
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spi_prettyprint_status_register_st_m25p(status);
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break;
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case MX_ID:
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if ((flash->model_id & 0xff00) == 0x2000)
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spi_prettyprint_status_register_st_m25p(status);
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break;
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case SST_ID:
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switch (flash->model_id) {
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case 0x2541:
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spi_prettyprint_status_register_sst25vf016(status);
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break;
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case 0x8d:
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case 0x258d:
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spi_prettyprint_status_register_sst25vf040b(status);
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break;
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default:
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spi_prettyprint_status_register_sst25(status);
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break;
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}
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break;
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}
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}
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|
|
|
int spi_chip_erase_60(struct flashchip *flash)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_CE_60_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_CE_60 },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_disable_blockprotect();
|
|
if (result) {
|
|
fprintf(stderr, "spi_disable_blockprotect failed\n");
|
|
return result;
|
|
}
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n",
|
|
__func__);
|
|
return result;
|
|
}
|
|
/* Wait until the Write-In-Progress bit is cleared.
|
|
* This usually takes 1-85 s, so wait in 1 s steps.
|
|
*/
|
|
/* FIXME: We assume spi_read_status_register will never fail. */
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(1000 * 1000);
|
|
if (check_erased_range(flash, 0, flash->total_size * 1024)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int spi_chip_erase_c7(struct flashchip *flash)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_CE_C7_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_CE_C7 },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_disable_blockprotect();
|
|
if (result) {
|
|
fprintf(stderr, "spi_disable_blockprotect failed\n");
|
|
return result;
|
|
}
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n", __func__);
|
|
return result;
|
|
}
|
|
/* Wait until the Write-In-Progress bit is cleared.
|
|
* This usually takes 1-85 s, so wait in 1 s steps.
|
|
*/
|
|
/* FIXME: We assume spi_read_status_register will never fail. */
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(1000 * 1000);
|
|
if (check_erased_range(flash, 0, flash->total_size * 1024)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int spi_chip_erase_60_c7(struct flashchip *flash)
|
|
{
|
|
int result;
|
|
result = spi_chip_erase_60(flash);
|
|
if (result) {
|
|
printf_debug("spi_chip_erase_60 failed, trying c7\n");
|
|
result = spi_chip_erase_c7(flash);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_BE_52_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n",
|
|
__func__);
|
|
return result;
|
|
}
|
|
/* Wait until the Write-In-Progress bit is cleared.
|
|
* This usually takes 100-4000 ms, so wait in 100 ms steps.
|
|
*/
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(100 * 1000);
|
|
if (check_erased_range(flash, addr, blocklen)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Block size is usually
|
|
* 64k for Macronix
|
|
* 32k for SST
|
|
* 4-32k non-uniform for EON
|
|
*/
|
|
int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_BE_D8_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n", __func__);
|
|
return result;
|
|
}
|
|
/* Wait until the Write-In-Progress bit is cleared.
|
|
* This usually takes 100-4000 ms, so wait in 100 ms steps.
|
|
*/
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(100 * 1000);
|
|
if (check_erased_range(flash, addr, blocklen)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int spi_chip_erase_d8(struct flashchip *flash)
|
|
{
|
|
int i, rc = 0;
|
|
int total_size = flash->total_size * 1024;
|
|
int erase_size = 64 * 1024;
|
|
|
|
spi_disable_blockprotect();
|
|
|
|
printf("Erasing chip: \n");
|
|
|
|
for (i = 0; i < total_size / erase_size; i++) {
|
|
rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
|
|
if (rc) {
|
|
fprintf(stderr, "Error erasing block at 0x%x\n", i);
|
|
break;
|
|
}
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
return rc;
|
|
}
|
|
|
|
/* Sector size is usually 4k, though Macronix eliteflash has 64k */
|
|
int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_SE_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n",
|
|
__func__);
|
|
return result;
|
|
}
|
|
/* Wait until the Write-In-Progress bit is cleared.
|
|
* This usually takes 15-800 ms, so wait in 10 ms steps.
|
|
*/
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(10 * 1000);
|
|
if (check_erased_range(flash, addr, blocklen)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
|
|
{
|
|
if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
|
|
fprintf(stderr, "%s called with incorrect arguments\n",
|
|
__func__);
|
|
return -1;
|
|
}
|
|
return spi_chip_erase_60(flash);
|
|
}
|
|
|
|
int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
|
|
{
|
|
if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
|
|
fprintf(stderr, "%s called with incorrect arguments\n",
|
|
__func__);
|
|
return -1;
|
|
}
|
|
return spi_chip_erase_c7(flash);
|
|
}
|
|
|
|
int spi_write_status_enable(void)
|
|
{
|
|
const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
|
|
int result;
|
|
|
|
/* Send EWSR (Enable Write Status Register). */
|
|
result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
|
|
|
|
if (result)
|
|
fprintf(stderr, "%s failed\n", __func__);
|
|
|
|
return result;
|
|
}
|
|
|
|
/*
|
|
* This is according the SST25VF016 datasheet, who knows it is more
|
|
* generic that this...
|
|
*/
|
|
int spi_write_status_register(int status)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_EWSR_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_EWSR },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_WRSR_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n",
|
|
__func__);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
int spi_byte_program(int addr, uint8_t byte)
|
|
{
|
|
int result;
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n",
|
|
__func__);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
int spi_nbyte_program(int address, uint8_t *bytes, int len)
|
|
{
|
|
int result;
|
|
/* FIXME: Switch to malloc based on len unless that kills speed. */
|
|
unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
|
|
JEDEC_BYTE_PROGRAM,
|
|
(address >> 16) & 0xff,
|
|
(address >> 8) & 0xff,
|
|
(address >> 0) & 0xff,
|
|
};
|
|
struct spi_command cmds[] = {
|
|
{
|
|
.writecnt = JEDEC_WREN_OUTSIZE,
|
|
.writearr = (const unsigned char[]){ JEDEC_WREN },
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
|
|
.writearr = cmd,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}, {
|
|
.writecnt = 0,
|
|
.writearr = NULL,
|
|
.readcnt = 0,
|
|
.readarr = NULL,
|
|
}};
|
|
|
|
if (!len) {
|
|
fprintf(stderr, "%s called for zero-length write\n", __func__);
|
|
return 1;
|
|
}
|
|
if (len > 256) {
|
|
fprintf(stderr, "%s called for too long a write\n", __func__);
|
|
return 1;
|
|
}
|
|
|
|
memcpy(&cmd[4], bytes, len);
|
|
|
|
result = spi_send_multicommand(cmds);
|
|
if (result) {
|
|
fprintf(stderr, "%s failed during command execution\n",
|
|
__func__);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
int spi_disable_blockprotect(void)
|
|
{
|
|
uint8_t status;
|
|
int result;
|
|
|
|
status = spi_read_status_register();
|
|
/* If there is block protection in effect, unprotect it first. */
|
|
if ((status & 0x3c) != 0) {
|
|
printf_debug("Some block protection in effect, disabling\n");
|
|
result = spi_write_status_register(status & ~0x3c);
|
|
if (result) {
|
|
fprintf(stderr, "spi_write_status_register failed\n");
|
|
return result;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int spi_nbyte_read(int address, uint8_t *bytes, int len)
|
|
{
|
|
const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
|
|
JEDEC_READ,
|
|
(address >> 16) & 0xff,
|
|
(address >> 8) & 0xff,
|
|
(address >> 0) & 0xff,
|
|
};
|
|
|
|
/* Send Read */
|
|
return spi_send_command(sizeof(cmd), len, cmd, bytes);
|
|
}
|
|
|
|
/*
|
|
* Read a complete flash chip.
|
|
* Each page is read separately in chunks with a maximum size of chunksize.
|
|
*/
|
|
int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
|
|
{
|
|
int rc = 0;
|
|
int i, j, starthere, lenhere;
|
|
int page_size = flash->page_size;
|
|
int toread;
|
|
|
|
/* Warning: This loop has a very unusual condition and body.
|
|
* The loop needs to go through each page with at least one affected
|
|
* byte. The lowest page number is (start / page_size) since that
|
|
* division rounds down. The highest page number we want is the page
|
|
* where the last byte of the range lives. That last byte has the
|
|
* address (start + len - 1), thus the highest page number is
|
|
* (start + len - 1) / page_size. Since we want to include that last
|
|
* page as well, the loop condition uses <=.
|
|
*/
|
|
for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
|
|
/* Byte position of the first byte in the range in this page. */
|
|
/* starthere is an offset to the base address of the chip. */
|
|
starthere = max(start, i * page_size);
|
|
/* Length of bytes in the range in this page. */
|
|
lenhere = min(start + len, (i + 1) * page_size) - starthere;
|
|
for (j = 0; j < lenhere; j += chunksize) {
|
|
toread = min(chunksize, lenhere - j);
|
|
rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
|
|
if (rc)
|
|
break;
|
|
}
|
|
if (rc)
|
|
break;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
|
|
{
|
|
if (!spi_programmer[spi_controller].read) {
|
|
fprintf(stderr, "%s called, but SPI read is unsupported on this"
|
|
" hardware. Please report a bug.\n", __func__);
|
|
return 1;
|
|
}
|
|
|
|
return spi_programmer[spi_controller].read(flash, buf, start, len);
|
|
}
|
|
|
|
/*
|
|
* Program chip using byte programming. (SLOW!)
|
|
* This is for chips which can only handle one byte writes
|
|
* and for chips where memory mapped programming is impossible
|
|
* (e.g. due to size constraints in IT87* for over 512 kB)
|
|
*/
|
|
int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
|
|
{
|
|
int total_size = 1024 * flash->total_size;
|
|
int i;
|
|
|
|
spi_disable_blockprotect();
|
|
/* Erase first */
|
|
printf("Erasing flash before programming... ");
|
|
if (erase_flash(flash)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
printf("done.\n");
|
|
for (i = 0; i < total_size; i++) {
|
|
spi_byte_program(i, buf[i]);
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(10);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Program chip using page (256 bytes) programming.
|
|
* Some SPI masters can't do this, they use single byte programming instead.
|
|
*/
|
|
int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
|
|
{
|
|
if (!spi_programmer[spi_controller].write_256) {
|
|
fprintf(stderr, "%s called, but SPI page write is unsupported "
|
|
" on this hardware. Please report a bug.\n", __func__);
|
|
return 1;
|
|
}
|
|
|
|
return spi_programmer[spi_controller].write_256(flash, buf);
|
|
}
|
|
|
|
uint32_t spi_get_valid_read_addr(void)
|
|
{
|
|
/* Need to return BBAR for ICH chipsets. */
|
|
return 0;
|
|
}
|
|
|
|
int spi_aai_write(struct flashchip *flash, uint8_t *buf)
|
|
{
|
|
uint32_t pos = 2, size = flash->total_size * 1024;
|
|
unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
|
|
int result;
|
|
|
|
switch (spi_controller) {
|
|
case SPI_CONTROLLER_WBSIO:
|
|
fprintf(stderr, "%s: impossible with Winbond SPI masters,"
|
|
" degrading to byte program\n", __func__);
|
|
return spi_chip_write_1(flash, buf);
|
|
default:
|
|
break;
|
|
}
|
|
if (erase_flash(flash)) {
|
|
fprintf(stderr, "ERASE FAILED!\n");
|
|
return -1;
|
|
}
|
|
result = spi_write_enable();
|
|
if (result)
|
|
return result;
|
|
spi_send_command(6, 0, w, NULL);
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(5); /* SST25VF040B Tbp is max 10us */
|
|
while (pos < size) {
|
|
w[1] = buf[pos++];
|
|
w[2] = buf[pos++];
|
|
spi_send_command(3, 0, w, NULL);
|
|
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
|
|
programmer_delay(5); /* SST25VF040B Tbp is max 10us */
|
|
}
|
|
spi_write_disable();
|
|
return 0;
|
|
}
|