mirror of
https://review.coreboot.org/flashrom.git
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2822888c81
SPI bitbanging on devices which speak SPI natively has a dual-use problem: We need to shut down normal SPI operations to do the bitbanging ourselves. Once we're done, it makes a lot of sense to reenable "normal" SPI operations again. Add request_bus/release_bus functions to struct bitbang_spi_master. Add a bitbang shutdown function (not used yet). Change MCP SPI and Intel NIC SPI to use the new request/release bus infrastructure. Cosmetic changes to a few error messages (80 column limit). There are multiple possible strategies for bus request/release: - Request at the start of a SPI command, release immediately afterwards. - Request at the start of a SPI multicommand, release once all commands of the multicommand are done. - Request on programmer init, release on shutdown. Each strategy has its own advantages. For now, we will stay with the first strategy which worked fine so far. Corresponding to flashrom svn r1171. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
180 lines
4.3 KiB
C
180 lines
4.3 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010 Carl-Daniel Hailfinger
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* Copyright (C) 2010 Idwer Vollering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Datasheet:
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* PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
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* 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
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* http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
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*/
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define EECD 0x10
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#define FLA 0x1c
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/*
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* Register bits of EECD.
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*
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* Bit 04, 05: FWE (Flash Write Enable Control)
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* 00b = not allowed
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* 01b = flash writes disabled
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* 10b = flash writes enabled
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* 11b = not allowed
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*/
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#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
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#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
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/* Flash Access register bits */
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/* Table 13-9 */
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#define FL_SCK 0
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#define FL_CS 1
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#define FL_SI 2
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#define FL_SO 3
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#define FL_REQ 4
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#define FL_GNT 5
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/* Currently unused */
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// #define FL_BUSY 30
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// #define FL_ER 31
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uint8_t *nicintel_spibar;
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const struct pcidev_status nics_intel_spi[] = {
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{PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
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{},
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};
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static void nicintel_request_spibus(void)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + FLA);
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tmp |= 1 << FL_REQ;
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pci_mmio_writel(tmp, nicintel_spibar + FLA);
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/* Wait until we are allowed to use the SPI bus. */
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while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ;
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}
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static void nicintel_release_spibus(void)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + FLA);
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tmp &= ~(1 << FL_REQ);
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pci_mmio_writel(tmp, nicintel_spibar + FLA);
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}
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static void nicintel_bitbang_set_cs(int val)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + FLA);
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tmp &= ~(1 << FL_CS);
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tmp |= (val << FL_CS);
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pci_mmio_writel(tmp, nicintel_spibar + FLA);
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}
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static void nicintel_bitbang_set_sck(int val)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + FLA);
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tmp &= ~(1 << FL_SCK);
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tmp |= (val << FL_SCK);
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pci_mmio_writel(tmp, nicintel_spibar + FLA);
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}
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static void nicintel_bitbang_set_mosi(int val)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + FLA);
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tmp &= ~(1 << FL_SI);
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tmp |= (val << FL_SI);
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pci_mmio_writel(tmp, nicintel_spibar + FLA);
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}
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static int nicintel_bitbang_get_miso(void)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + FLA);
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tmp = (tmp >> FL_SO) & 0x1;
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return tmp;
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}
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static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
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.type = BITBANG_SPI_MASTER_NICINTEL,
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.set_cs = nicintel_bitbang_set_cs,
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.set_sck = nicintel_bitbang_set_sck,
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.set_mosi = nicintel_bitbang_set_mosi,
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.get_miso = nicintel_bitbang_get_miso,
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.request_bus = nicintel_request_spibus,
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.release_bus = nicintel_release_spibus,
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};
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int nicintel_spi_init(void)
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{
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uint32_t tmp;
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get_io_perms();
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io_base_addr = pcidev_init(PCI_VENDOR_ID_INTEL, PCI_BASE_ADDRESS_0,
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nics_intel_spi);
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nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",
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io_base_addr, 4096);
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tmp = pci_mmio_readl(nicintel_spibar + EECD);
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tmp &= ~FLASH_WRITES_DISABLED;
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tmp |= FLASH_WRITES_ENABLED;
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pci_mmio_writel(tmp, nicintel_spibar + EECD);
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/* 1 usec halfperiod delay for now. */
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if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1))
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return 1;
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buses_supported = CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_NICINTEL;
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return 0;
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}
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int nicintel_spi_shutdown(void)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(nicintel_spibar + EECD);
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tmp &= ~FLASH_WRITES_ENABLED;
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tmp |= FLASH_WRITES_DISABLED;
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pci_mmio_writel(tmp, nicintel_spibar + EECD);
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physunmap(nicintel_spibar, 4096);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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