mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 15:12:36 +02:00
00e02a6184
CH347 SPI interface supports up to 60M. For example, to set a 30M spi rate, use -p ch347_spi:spispeed=30M. Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Signed-off-by: ZhiYuanNJ Liu <871238103@qq.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82776 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>